公开(公告)号：US11295821B2

公开(公告)日：2022-04-05

申请号：US17160754

申请日：2021-01-28

Applicant: KIOXIA CORPORATION

Inventor： Shinya Okuno ,  Shigeki Nagasaka ,  Toshiyuki Kouchi

IPC: G11C16/04 ,  G11C16/32 ,  G11C16/26 ,  G11C16/16 ,  G11C16/12 ,  G11C7/02 ,  G11C7/10 ,  G11C16/10 ,  G06F5/06 ,  G06F13/16

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

公开(公告)号：US11270981B2

公开(公告)日：2022-03-08

申请号：US17023617

申请日：2020-09-17

Applicant: KIOXIA CORPORATION

Inventor： Mikihiko Ito ,  Masaru Koyanagi ,  Masafumi Nakatani ,  Shinya Okuno ,  Shigeki Nagasaka ,  Masahiro Yoshihara ,  Akira Umezawa ,  Satoshi Tsukiyama ,  Kazushige Kawasaki

IPC: G11C16/30 ,  H01L25/065 ,  G11C16/10 ,  G11C16/14 ,  G11C16/32 ,  G11C16/26 ,  H01L27/10 ,  G11C16/08 ,  G11C16/12 ,  G11C16/34 ,  G11C16/04

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

公开(公告)号：US12100459B2

公开(公告)日：2024-09-24

申请号：US18333661

申请日：2023-06-13

Applicant: KIOXIA CORPORATION

Inventor： Shinya Okuno ,  Shigeki Nagasaka ,  Toshiyuki Kouchi

IPC: G11C16/04 ,  G06F5/06 ,  G06F13/16 ,  G11C7/02 ,  G11C7/10 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C16/32 ,  G06F5/06 ,  G06F13/1673 ,  G11C7/02 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G06F2205/067 ,  G11C16/0483 ,  G11C2207/108 ,  G11C2207/2281 ,  Y02D10/00

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

公开(公告)号：US12197732B2

公开(公告)日：2025-01-14

申请号：US17898370

申请日：2022-08-29

Applicant: KIOXIA CORPORATION

Inventor： Kenta Shibasaki ,  Yoshihiko Shindo ,  Yasuhiro Hirashima ,  Akio Sugahara ,  Shigeki Nagasaka ,  Dai Nakamura ,  Yousuke Hagiwara

IPC: G06F3/06

Abstract: A memory system includes a memory chip and a memory controller. The memory chip includes a storage region that stores setup data used for setup of the memory chip during power on thereof. The memory controller is configured to determine whether or not the memory controller has the setup data, when determining that the memory controller does not have the setup data, instruct the memory chip to read the setup data from the storage region and perform a first setup operation based on the read setup data, and when determining that the memory controller has the setup data, transmit the setup data to the memory chip and instruct the memory chip to perform a second setup operation based on the setup data received from the memory controller.

公开(公告)号：US11715529B2

公开(公告)日：2023-08-01

申请号：US17689300

申请日：2022-03-08

Applicant: KIOXIA CORPORATION

Inventor： Shinya Okuno ,  Shigeki Nagasaka ,  Toshiyuki Kouchi

IPC: G11C16/04 ,  G11C16/32 ,  G11C16/26 ,  G11C16/16 ,  G11C16/12 ,  G11C7/02 ,  G11C7/10 ,  G11C16/10 ,  G06F5/06 ,  G06F13/16

CPC classification number: G11C16/32 ,  G06F5/06 ,  G06F13/1673 ,  G11C7/02 ,  G11C7/106 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1066 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G06F2205/067 ,  G11C16/0483 ,  G11C2207/108 ,  G11C2207/2281 ,  Y02D10/00

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.