公开(公告)号：US20160359110A1

公开(公告)日：2016-12-08

申请号：US15120993

申请日：2015-02-18

Applicant: NEC CORPORATION

Inventor： Naoki BANNO ,  Munehiro TADA ,  Koichiro OKAMOTO

IPC: H01L45/00 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L45/1266 ,  G11C13/0007 ,  G11C13/0011 ,  G11C2213/15 ,  G11C2213/52 ,  H01L23/5226 ,  H01L23/53228 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1633 ,  H01L45/1675

Abstract: Provided is a nonvolatile switching element which has high retention ability even if programmed at a low current, while being suppressed in dielectric breakdown of a variable resistance layer during a reset operation. This switching element is provided with: a first electrode; a second electrode; and a variable resistance layer that is arranged between the first electrode and the second electrode and has ion conductivity. The first electrode contains a metal which generates metal ions that can be conducted in the variable resistance layer. The second electrode is provided with: a first electrode layer that is formed in contact with the variable resistance layer; and a second electrode layer that is formed in contact with the first electrode layer. The first electrode layer is formed of a ruthenium alloy that contains ruthenium and a first metal having a larger standard Gibbs energy of formation of oxide than ruthenium in the negative direction. The second electrode layer is formed of a nitride that contains the first metal. The content of the first metal in the first electrode layer is lower than the content of the first metal in the second electrode layer.

Abstract translation: 提供了即使在低电流下编程也具有高保持能力的非易失性开关元件，同时在复位操作期间抑制可变电阻层的电介质击穿。 该开关元件设置有：第一电极; 第二电极; 以及布置在第一电极和第二电极之间并具有离子传导性的可变电阻层。 第一电极含有产生可在可变电阻层中传导的金属离子的金属。 第二电极设置有：与可变电阻层接触形成的第一电极层; 以及形成为与第一电极层接触的第二电极层。 第一电极层由含有钌的钌合金和在负方向上具有比钌形成氧化物更大的标准吉布斯能量的第一金属形成。 第二电极层由含有第一金属的氮化物形成。 第一电极层中的第一金属的含量低于第二电极层中的第一金属的含量。

公开(公告)号：US20160358641A1

公开(公告)日：2016-12-08

申请号：US15237434

申请日：2016-08-15

Applicant: Micron Technology, Inc.

Inventor： Roy E. Meade

IPC: G11C11/24 ,  G11C11/56 ,  H01L49/02 ,  H01L45/00 ,  H01L27/10 ,  G11C11/34 ,  G11C13/00

CPC classification number: G11C11/24 ,  G11C8/08 ,  G11C11/34 ,  G11C11/56 ,  G11C11/565 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  H01L27/101 ,  H01L28/40 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233

Abstract: Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.

公开(公告)号：US09502102B1

公开(公告)日：2016-11-22

申请号：US14341726

申请日：2014-07-25

Applicant: Crossbar, Inc.

Inventor： Tanmay Kumar ,  Sung Hyun Jo

IPC: G11C13/02 ,  G11C11/56 ,  H01L45/00 ,  G11C13/00

CPC classification number: G11C11/5692 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0069 ,  G11C17/165 ,  G11C17/18 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/52 ,  G11C2213/73 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: Providing for a memory cell capable of forming a one time programmable, multi-level cell two-terminal memory cell or a rewritable, two terminal memory cell is described herein. In some embodiments, one time programmable, multi-level cell two-terminal memory cell can exhibit diode-like characteristics. In other embodiments, the memory cell can comprise a first electrode layer configured to generate ions in response to an electric field applied to the memory cell; a resistive ion migration layer at least in part permeable to migration of the ions within the resistive ion migration layer; a second electrode layer; and a substrate layer comprising a silicon wafer.

Abstract translation: 提供能够形成一次可编程的多电平单元两端存储器单元或可重写的两端存储单元的存储单元。 在一些实施例中，一次可编程的多电平单元两端存储器单元可以表现出二极管状特性。 在其他实施例中，存储器单元可以包括配置成响应于施加到存储器单元的电场而产生离子的第一电极层; 电阻离子迁移层至少部分可透过电离离子迁移层内的离子迁移; 第二电极层; 以及包括硅晶片的基底层。

公开(公告)号：US20160322104A1

公开(公告)日：2016-11-03

申请号：US15205882

申请日：2016-07-08

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

IPC: G11C13/00

CPC classification number: G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/24 ,  G11C2213/71

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

公开(公告)号：US09484088B2

公开(公告)日：2016-11-01

申请号：US14665794

申请日：2015-03-23

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills

IPC: G11C5/02 ,  G11C5/06 ,  G11C13/00 ,  G11C11/00 ,  G11C11/50 ,  G11C7/18 ,  G11C8/00 ,  G11C11/56 ,  G11C8/14 ,  G11C19/00

CPC classification number: G11C13/0011 ,  G11C5/02 ,  G11C5/06 ,  G11C7/18 ,  G11C8/00 ,  G11C8/14 ,  G11C11/00 ,  G11C11/50 ,  G11C11/56 ,  G11C11/5614 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0069 ,  G11C19/00 ,  G11C2213/52

Abstract: Various embodiments include at least one resistance change memory (RCM) cell, In one embodiment, three or more pairs of electrical contacts are coupled to the at least one RCM cell. A first portion of the pairs are arranged laterally to one another in a first grouping and a second opposing portion of the pairs are arranged laterally to one another in a second grouping. A memory cell material is disposed between opposing sides of the pairs of the three or more electrical contacts. The memory cell material is configured to form a conductive pathway between one or more of the pairs, with each of the three or more pairs being configured to be accessed individually for at least one operation including program, erase, and read operations. Additional apparatuses and methods are described.

Abstract translation: 各种实施例包括至少一个电阻变化存储器（RCM）单元。在一个实施例中，三个或更多对电触点耦合到至少一个RCM单元。 成对的第一部分在第一组中彼此横向地布置，并且对的第二相对部分在第二组中彼此横向地布置。 存储单元材料设置在三个或更多个电触点对的相对侧之间。 存储单元材料被配置为在一对或多对之间形成导电路径，其中三对或更多对中的每一对被配置为分别访问包括程序，擦除和读取操作的至少一个操作。 描述附加的装置和方法。

公开(公告)号：US09472272B2

公开(公告)日：2016-10-18

申请号：US14628280

申请日：2015-02-22

Applicant: Adesto Technologies Corporation

Inventor： Venkatesh P. Gopinath ,  Deepak Kamalanathan ,  Daniel Wang

IPC: G11C13/00

CPC classification number: G11C13/0011 ,  G11C13/0002 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/74 ,  G11C2213/79

Abstract: In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) a word line pair configured to control access to the programmable impedance element, where the word line pair comprises first and second word lines; (iii) a PMOS transistor having a source coupled to the cathode, a drain coupled to a bit line, and a gate coupled to the first word line; and (iv) an NMOS transistor having a source coupled to the bit line, a drain coupled to the cathode, and a gate coupled to the second word line.

Abstract translation: 在一个实施例中，半导体存储器件包括多个电阻式开关存储器单元，其中每个电阻式开关存储器单元可以包括：（i）具有阳极和阴极的可编程阻抗元件; （ii）被配置为控制对所述可编程阻抗元件的访问的字线对，其中所述字线对包括第一和第二字线; （iii）具有耦合到阴极的源极，耦合到位线的漏极和耦合到第一字线的栅极的PMOS晶体管; 以及（iv）具有耦合到所述位线的源极，耦合到所述阴极的漏极和耦合到所述第二字线的栅极的NMOS晶体管。

公开(公告)号：US20160299843A1

公开(公告)日：2016-10-13

申请号：US14682078

申请日：2015-04-08

Applicant: Nanya Technology Corp.

Inventor： Da-Zen Chuang ,  Chi-Hsiang Kuo

IPC: G06F12/06 ,  G11C7/10 ,  G11C14/00 ,  G06F12/02

CPC classification number: G11C11/16 ,  G06F12/0238 ,  G06F2212/1032 ,  G06F2212/1056 ,  G06F2212/202 ,  G06F2212/205 ,  G11C11/005 ,  G11C11/22 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0011 ,  Y02D10/13

Abstract: Discloses is a unified non-volatile memory comprising: a first memory section, served as a read only memory; and a second memory section, served as a random access memory. An electronic apparatus applying the unified non-volatile memory is also disclosed.

Abstract translation: 公开了一种统一的非易失性存储器，包括：第一存储器部分，用作只读存储器; 以及作为随机存取存储器的第二存储器部分。 还公开了应用统一的非易失性存储器的电子设备。

公开(公告)号：US20160293584A1

公开(公告)日：2016-10-06

申请号：US15185004

申请日：2016-06-16

Applicant: Guobiao ZHANG

Inventor： Guobiao ZHANG

IPC: H01L25/065 ,  H01L25/18 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C13/00 ,  G11C16/26

CPC classification number: H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  G11C5/145 ,  G11C8/14 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C2029/0411 ,  G11C2213/71 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/13101 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: The present invention discloses a three-dimensional vertical memory (3D-MV). It comprises at least a 3D-array die and at least a peripheral-circuit die. The 3D-array die comprises a plurality of vertical memory strings. The number of interconnect levels in the peripheral-circuit die is more than the number of interconnect levels in the 3D-array die, but substantially less than the number of memory cells on each of the vertical memory strings in the 3D-array die.

Abstract translation: 本发明公开了一种立体垂直存储器（3D-MV）。 它包括至少一个3D阵列管芯和至少一个外围电路管芯。 3D阵列管芯包括多个垂直存储器串。 外围电路管芯中的互连级别的数量大于3D阵列管芯中的互连级别的数量，但是基本上小于3D阵列管芯中的每个垂直存储器串上的存储器单元的数量。

公开(公告)号：US09443584B2

公开(公告)日：2016-09-13

申请号：US13716357

申请日：2012-12-17

Applicant: ADESTO TECHNOLOGIES CORPORATION

Inventor： Ravi Sunkavalli ,  Malcolm Wing

IPC: G06F13/40 ,  G06F11/00 ,  G11C13/00 ,  G06F15/16 ,  G06F15/177

CPC classification number: G11C13/0011 ,  G06F13/4027 ,  G06F13/4068 ,  G06F15/177

Abstract: Structures and methods for improving logging in network structures are disclosed herein. In one embodiment, an apparatus can include: (i) a network interface card (NIC) configured to receive data, to transmit data, and to send data for logging; (ii) a memory log coupled to the NIC, where the memory log comprises non-volatile memory (NVM) configured to write the data sent for logging from the NIC; and (iii) where the data being sent for logging by the memory log occurs substantially simultaneously with the data being received by the NIC, and the data being transmitted from the NIC.

Abstract translation: 本文公开了用于改善网络结构记录的结构和方法。 在一个实施例中，设备可以包括：（i）网络接口卡（NIC），被配置为接收数据，传输数据和发送用于记录的数据; （ii）耦合到所述NIC的存储器日志，其中所述存储器日志包括被配置为写入从所述NIC发送来记录的数据的非易失性存储器（NVM） 和（iii）其中由存储器日志发送用于记录的数据基本上与由NIC接收的数据同时发生，并且数据从NIC发送。

公开(公告)号：US09431607B2

公开(公告)日：2016-08-30

申请号：US14669279

申请日：2015-03-26

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Gabriel Molas ,  Philippe Blaise ,  Faiz Dahmani ,  Rémy Gassiloud ,  Elisa Vianello

IPC: H01L29/04 ,  H01L47/00 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L45/146 ,  G11C13/0011 ,  G11C2213/32 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266

Abstract: A resistive random access memory device includes a first electrode made of inert material; a second electrode made of soluble material, and a solid electrolyte, the first and second electrodes being respectively in contact with one of the faces of the electrolyte, the second electrode to supply mobile ions circulating in the solid electrolyte to the first electrode to form a conductive filament between the first and second electrodes when a voltage is applied between the first and second electrodes, the solid electrolyte including a region made of a first metal oxide that is doped by a second metal, distinct from the first metal and able to form a second metal oxide, the second metal selected such that the first metal oxide doped by the second metal has a band gap energy less than or equal to that of the first metal oxide not doped by the second metal.

Abstract translation: 电阻式随机存取存储器件包括由惰性材料制成的第一电极; 由可溶性材料制成的第二电极和固体电解质，所述第一和第二电极分别与所述电解质的一个面接触，所述第二电极将在所述固体电解质中循环的流动离子供应到所述第一电极，以形成 当在第一和第二电极之间施加电压时，第一和第二电极之间的导电细丝，固体电解质包括由与第一金属不同的第二金属掺杂的第一金属氧化物制成的区域，并且能够形成 第二金属氧化物，第二金属被选择为使得由第二金属掺杂的第一金属氧化物的带隙能量小于或等于没有被第二金属掺杂的第一金属氧化物的带隙能量。