公开(公告)号：US09704639B2

公开(公告)日：2017-07-11

申请号：US14536103

申请日：2014-11-07

申请人： Solantro Semiconductor Corp.

发明人： Raymond Kenneth Orr ,  James Benson Bacque ,  Mark Roy Harris

IPC分类号： H01L23/495 ,  H01L23/64 ,  H01L23/48 ,  H01F27/28 ,  H01L23/00 ,  H01L21/48 ,  H01F27/29 ,  H01F27/30 ,  H01L23/522 ,  H01L23/66

CPC分类号： H01F27/2804 ,  H01F27/2852 ,  H01F27/29 ,  H01F27/303 ,  H01F2027/2819 ,  H01L21/4842 ,  H01L23/495 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49544 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/48177 ,  H01L2924/00014 ,  H01L2924/1711 ,  H01L2924/1715 ,  H01L2924/173 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2224/45099

摘要： The present disclosure relates to non-planar inductive electrical elements in semiconductor package lead frames. A non-planar inductive element is formed from a lead frame in a semiconductor package. The semiconductor package also includes at least one semiconductor die coupled to the lead frame. The non-planar inductive element could be formed by deforming portions of a patterned planar lead frame blank to form the non-planar inductive element in a deformed lead frame blank. The deformed lead frame blank and the at least one semiconductor die could then be packaged into a semiconductor package. A setting tool could be used to deform the lead frame blank. A configurable lead frame blank could be configurable into any of a variety of inductive elements, through interconnection of lead frame segments using wire bonds, for example.

公开(公告)号：USRE46466E1

公开(公告)日：2017-07-04

申请号：US12712934

申请日：2010-02-25

申请人： Bernhard P. Lange ,  Anthony L. Coyle ,  Quang X. Mai

发明人： Bernhard P. Lange ,  Anthony L. Coyle ,  Quang X. Mai

IPC分类号： H01L21/82 ,  H01L21/44 ,  H01L23/532 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31

CPC分类号： H01L23/53238 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13013 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14133 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/81191 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/8146 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/01028 ,  H01L2224/05193 ,  H01L2924/013 ,  H01L2924/00

摘要： A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

公开(公告)号：US09691739B2

公开(公告)日：2017-06-27

申请号：US15061444

申请日：2016-03-04

申请人： Tessera Advanced Technologies, Inc.

发明人： Michihiro Kawashita ,  Yasuhiro Yoshimura ,  Naotaka Tanaka ,  Takahiro Naito ,  Takashi Akazawa

IPC分类号： H01L21/00 ,  H01L25/065 ,  H01L21/683 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L23/522 ,  H01L23/528 ,  H01L25/07

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13009 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16058 ,  H01L2224/16112 ,  H01L2224/16146 ,  H01L2224/274 ,  H01L2224/81136 ,  H01L2224/81345 ,  H01L2224/81365 ,  H01L2224/81801 ,  H01L2224/81898 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1451 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a first semiconductor substrate having a first surface and a second surface opposite the first surface, a first insulating film formed on the first surface, a first hole formed in the first insulating film and partially extending into the first semiconductor substrate, a second hole formed in the second surface, a first electrode entirely filling the first hole, and a conductive film conformally formed in the second hole. The conductive film is electrically connected to a bottom surface of the first electrode and leaves a third hole in the first semiconductor substrate open. The third hole is configured to receive a second electrode of a second semiconductor substrate.

公开(公告)号：US09661752B2

公开(公告)日：2017-05-23

申请号：US13163200

申请日：2011-06-17

申请人： Tao Hong ,  Markus Thoben

发明人： Tao Hong ,  Markus Thoben

IPC分类号： H05K7/00 ,  H05K1/18 ,  G01R1/20 ,  H01L23/64 ,  H01L25/07 ,  H01L25/16 ,  H01L25/18 ,  H01L23/00 ,  H01L27/02 ,  H01L49/02 ,  H05K3/22

CPC分类号： H05K1/181 ,  G01R1/203 ,  H01L23/647 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L27/0207 ,  H01L28/20 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H05K3/222 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10022 ,  H05K2201/10166 ,  H05K2203/173 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/83205

摘要： A circuit arrangement has a populated circuit carrier and includes a flat insulation carrier having a top side and a patterned metallization layer on the top side and a first power semiconductor chip arranged on a first section of the metallization layer. The first power semiconductor chip has a first lower chip load terminal electrically conductively connected to the first section. A shunt resistor is arranged on a second section of the metallization layer. The shunt resistor has a lower main terminal electrically conductively connected to the second section. An electrically conductive connection is provided between the first section and the second section. The electrically conductive connection includes a constriction between the first section and the second section so that a current which flows between the first lower chip load terminal and the lower main terminal during operation of the circuit arrangement must pass through the constriction.

公开(公告)号：US09653389B2

公开(公告)日：2017-05-16

申请号：US15237310

申请日：2016-08-15

申请人： ROHM CO., LTD.

发明人： Kenichi Yoshimochi

IPC分类号： H01L23/495 ,  H05K7/14 ,  H01L23/31 ,  H01L25/11 ,  H01L25/07 ,  H01L29/78 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49805 ,  H01L24/29 ,  H01L24/30 ,  H01L24/33 ,  H01L24/36 ,  H01L24/37 ,  H01L24/39 ,  H01L24/40 ,  H01L24/41 ,  H01L25/072 ,  H01L25/074 ,  H01L25/117 ,  H01L29/78 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/40245 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K7/14 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

摘要： A module (1) includes a first functional device (2) and a second functional device (3). The first functional device (2) includes a base electrode, an emitter electrode and a collector electrode. The second functional device (3) includes at least one electrode. The module (1) further includes a conductive frame (4). One of the base electrode, the emitter electrode, and the collector electrode of the first functional device (2) is directly connected to the frame (4). The electrode of the second functional device (3) is also directly connected to the frame (4). The frame (4) includes a portion serving as a terminal for external connection.

公开(公告)号：US09622368B2

公开(公告)日：2017-04-11

申请号：US14400105

申请日：2012-08-24

申请人： Ryo Tsuda ,  Kazuhiro Morishita

发明人： Ryo Tsuda ,  Kazuhiro Morishita

IPC分类号： H01R13/46 ,  H05K5/00 ,  H05K7/02 ,  H01L23/498 ,  H01L25/11 ,  H01L23/04 ,  H01L25/10 ,  H01L25/18 ,  H05K1/02 ,  H01L23/373 ,  H01L23/24 ,  H01L23/00

CPC分类号： H05K7/02 ,  H01L23/04 ,  H01L23/24 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/105 ,  H01L25/115 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30107 ,  H05K1/0263 ,  H01L2924/00012 ,  H01L2924/00

摘要： Each of semiconductor module includes a semiconductor chip, a case surrounding the semiconductor chip, and a main electrode connected to the semiconductor chip and led out to an upper surface of case. A connecting electrode is connected and fixed to the main electrodes of the adjacent semiconductor modules. The connecting electrode is formed only of a metal plate.

公开(公告)号：US09620705B2

公开(公告)日：2017-04-11

申请号：US15049732

申请日：2016-02-22

申请人： ALLEGRO MICROSYSTEMS, LLC

发明人： Shaun D. Milano ,  Michael C. Doogue ,  William P. Taylor

IPC分类号： H01L23/00 ,  H01L43/04 ,  H01L23/495 ,  H01L23/31 ,  G01R33/00 ,  H01L43/02 ,  H01L43/12 ,  G01R33/07 ,  G01R33/09 ,  H01L43/06 ,  H01L43/08 ,  H01L43/14

CPC分类号： H01L43/04 ,  G01R33/0029 ,  G01R33/0052 ,  G01R33/0076 ,  G01R33/07 ,  G01R33/09 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49503 ,  H01L23/49506 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/17 ,  H01L43/02 ,  H01L43/06 ,  H01L43/065 ,  H01L43/08 ,  H01L43/12 ,  H01L43/14 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： Methods and apparatus to provide a magnetic field sensor device including a magnetic sensor element, a die having wafer bumps, wherein the magnetic sensor element is positioned in relation to the die, and conductive leadfingers having respective portions electrically connected to the wafer bumps. In embodiments, the device includes a region about the magnetic sensor element that does not contain electrically conductive material for preventing eddy current flow.

公开(公告)号：US09601418B2

公开(公告)日：2017-03-21

申请号：US14209569

申请日：2014-03-13

申请人： Infineon Technologies Americas Corp.

发明人： Eung San Cho ,  Chuan Cheah ,  Andrew N. Sawle

IPC分类号： H01L23/495 ,  H01L25/07 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L25/074 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source.

公开(公告)号：US20170079159A1

公开(公告)日：2017-03-16

申请号：US15265354

申请日：2016-09-14

申请人： ABB Schweiz AG

发明人： Tobias Schluer

IPC分类号： H05K7/20 ,  H02M1/08 ,  H02M7/00

CPC分类号： H05K7/209 ,  H01L23/642 ,  H01L25/115 ,  H01L2924/13055 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025 ,  H02M1/08 ,  H02M7/003 ,  H05K7/1432

摘要： A three-phase two-level power electronics assembly is disclosed in one form including a thermally conductive base plate, a heat dissipation unit, mounted on a first face of the base plate, connectors for three-phase AC output, chopper DC outputs, and two poles of a DC link, and a set of power electronics devices mounted on a second face of the base plate, whereby the power electronic devices are arranged within the three-phase two-level power electronics assembly in rows to provide a three phase AC output as well as chopper DC outputs and connected to the respective connectors, whereby the rows connected to the three-phase AC output and the rows connected to the chopper DC outputs are alternately arranged on the base plate. Also disclosed is a power converter, in particular a static power converter, having at least one three-phase two-level power electronics assembly as specified above.

摘要翻译： 公开了三相二电平电力电子组件，其一种形式包括安装在基板的第一面上的导热基板，散热单元，用于三相交流输出的连接器，斩波器直流输出和 DC链路的两极，以及安装在基板的第二面上的一组电力电子设备，由此电力电子设备被排列在三相二电平电力电子组件中，以提供三相AC 输出以及斩波直流输出并连接到相应的连接器，由此连接到三相AC输出的行和连接到斩波器DC输出的行交替地布置在基板上。 还公开了一种功率转换器，特别是具有如上所述的至少一个三相二电平电力电子组件的静态功率转换器。

公开(公告)号：US20170062020A1

公开(公告)日：2017-03-02

申请号：US15351580

申请日：2016-11-15

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Takafumi BETSUI ,  Naoto TAOKA ,  Motoo SUWA ,  Shigezumi MATSUI ,  Norihiko SUGITA ,  Yoshiharu FUKUSHIMA

IPC分类号： G11C5/04 ,  G11C5/06 ,  H01L25/18 ,  H01L23/00 ,  H05K1/18 ,  H01L23/498

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

摘要： A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.