公开(公告)号：USRE46466E1

公开(公告)日：2017-07-04

申请号：US12712934

申请日：2010-02-25

申请人： Bernhard P. Lange ,  Anthony L. Coyle ,  Quang X. Mai

发明人： Bernhard P. Lange ,  Anthony L. Coyle ,  Quang X. Mai

IPC分类号： H01L21/82 ,  H01L21/44 ,  H01L23/532 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31

CPC分类号： H01L23/53238 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13013 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14133 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/81191 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/8146 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/01028 ,  H01L2224/05193 ,  H01L2924/013 ,  H01L2924/00

摘要： A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

公开(公告)号：US07335536B2

公开(公告)日：2008-02-26

申请号：US11218408

申请日：2005-09-01

申请人： Bernhard P. Lange ,  Anthony L. Coyle ,  Quang X. Mai

发明人： Bernhard P. Lange ,  Anthony L. Coyle ,  Quang X. Mai

IPC分类号： H01L21/82 ,  H01L21/44

CPC分类号： H01L23/53238 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13013 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14133 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/81191 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/8146 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/01028 ,  H01L2224/05193 ,  H01L2924/013 ,  H01L2924/00

摘要： A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

摘要翻译： 一种用于制造用于大电流半导体倒装芯片产品的低电阻，低电感器件的方法。 制造了一种结构，其包括具有金属化迹线的半导体芯片，与迹线接触的铜线以及在每条线上以有序和重复布置的铜凸块，使得一条线的凸块位于相应凸块之间的中间 的相邻线。 提供了一种具有细长铜线的衬底，其具有第一和第二表面，引线与线成直角。 每个引线的第一表面使用焊料元件连接到相应的交变线的凸块。 最后，将组件封装在模制化合物中，使得第二引线表面保持未封装。

公开(公告)号：US07476976B2

公开(公告)日：2009-01-13

申请号：US11358668

申请日：2006-02-21

申请人： Bernhard P. Lange ,  Anthony L. Coyle

发明人： Bernhard P. Lange ,  Anthony L. Coyle

IPC分类号： H01L23/52 ,  H01L23/34

CPC分类号： H01L23/4334 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/5286 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/00 ,  H01L2924/2075 ,  H01L2924/2076 ,  H01L2924/20754 ,  H01L2924/00012 ,  H01L2224/05099

摘要： A QFN package and method of making same is provided comprising a substrate having a metal line extending from a connection element on a perimeter region of the substrate to a high current contact pad on interior region of the substrate. A semiconductor chip having an active surface generally faces the interior region of the substrate, wherein a heat-dissipating patterned metal distribution layer is formed over the active surface and electrically connected to an active component thereon. A solder strip electrically and thermally connects the high current contact pad and the metal distribution layer, and a mold compound generally encapsulates the semiconductor chip. The solder strip is generally uniform in depth and surface area, wherein low electrical resistance and inductance is provided between the high current contact pad and the metal distribution layer. An integrated heat sink may be further formed or placed on a passive surface of the chip.

摘要翻译： 提供了一种QFN封装及其制造方法，包括：具有从衬底的周边区域上的连接元件延伸到衬底的内部区域上的高电流接触焊盘的金属线的衬底。 具有活性表面的半导体芯片大致面向衬底的内部区域，其中散热图案化的金属分布层形成在活性表面上并与其上的活性组分电连接。 焊接电极电连接高电流接触焊盘和金属分布层，并且模制化合物通常封装半导体芯片。 焊料条的深度和表面积通常是均匀的，其中在高电流接触焊盘和金属分布层之间提供低电阻和电感。 集成散热器可以进一步形成或放置在芯片的被动表面上。

公开(公告)号：US20080102563A1

公开(公告)日：2008-05-01

申请号：US11554728

申请日：2006-10-31

申请人： Bernhard P. Lange ,  Anthony L. Coyle ,  Jeffrey Gail Holloway

发明人： Bernhard P. Lange ,  Anthony L. Coyle ,  Jeffrey Gail Holloway

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L21/561 ,  H01L21/4821 ,  H01L23/3121 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/341 ,  H05K2201/10689 ,  H05K2201/10931 ,  H05K2201/10969 ,  H05K2201/10984 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which further comprises a plurality of lead pads and a die pad. The method also includes forming a channel between the lead pads of nearby package sites without singulating the packages. Another step in the method includes disposing solder on the lead pads, the die pad, or the lead pads and the die pads without substantially covering the channel with solder. The manufacturing method further includes singulating the packages.

摘要翻译： 本文公开了一种制造半导体封装的方法，该半导体封装在引线焊盘上具有焊接位置，该焊盘抵达封装的边缘（非拉回引线）。 它包括将多个管芯封装在引线框架条上。 引线框架条包括多个封装位置，其还包括多个引线焊盘和管芯焊盘。 该方法还包括在附近的封装位置的引线焊盘之间形成通道，而不需要对封装进行分离。 该方法的另一步骤包括在焊盘，芯片焊盘或引线焊盘和裸片焊盘上布置焊料，而基本上不用焊料覆盖焊道。 制造方法还包括将包装分离。

公开(公告)号：US08039956B2

公开(公告)日：2011-10-18

申请号：US11210066

申请日：2005-08-22

申请人： Anthony L. Coyle ,  Bernhard P. Lange

发明人： Anthony L. Coyle ,  Bernhard P. Lange

IPC分类号： H01L29/40

CPC分类号： H01L23/49562 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/4951 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

摘要： A high current semiconductor device (for example QFN for 30 to 70 A) with low resistance and low inductance is encapsulated by molding compound (401, height 402 about 0.9 mm) so that the second lead surfaces 110b remain un-encapsulated. A copper heat slug (404) may be attached to chip surface (101b) using thermally conductive adhesive (403). Chip surface (101a), protected by an overcoat (103) has metallization traces (102). Copper-filled windows (107) contact the traces and copper layers (105) parallel to traces (102). Copper bumps (108) are formed on each line in an orderly and repetitive arrangement so that the bumps of one line are positioned about midway between the bumps of the neighboring lines. A substrate has elongated leads (110) oriented at right angles to the lines; the leads connect the corresponding bumps of alternating lines.

摘要翻译： 具有低电阻和低电感的高电流半导体器件（例如30至70A的QFN）通过模制化合物（401，高度402约0.9mm）被封装，使得第二引线表面110b保持未封装。 可以使用导热粘合剂（403）将铜热块（404）附接到切屑表面（101b）。 由外涂层（103）保护的芯片表面（101a）具有金属化迹线（102）。 铜填充窗（107）与平行于迹线（102）的迹线和铜层（105）接触。 在每条线上以有序且重复的布置形成铜凸块（108），使得一条线的凸起位于相邻线的凸块之间的中间。 衬底具有与线成直角定向的细长引线（110） 引线连接相应的交替线路的凸起。

公开(公告)号：US07608484B2

公开(公告)日：2009-10-27

申请号：US11554728

申请日：2006-10-31

申请人： Bernhard P. Lange ,  Anthony L. Coyle ,  Jeffrey Gail Holloway

发明人： Bernhard P. Lange ,  Anthony L. Coyle ,  Jeffrey Gail Holloway

IPC分类号： H01L21/00

CPC分类号： H01L21/561 ,  H01L21/4821 ,  H01L23/3121 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/341 ,  H05K2201/10689 ,  H05K2201/10931 ,  H05K2201/10969 ,  H05K2201/10984 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which further comprises a plurality of lead pads and a die pad. The method also includes forming a channel between the lead pads of nearby package sites without singulating the packages. Another step in the method includes disposing solder on the lead pads, the die pad, or the lead pads and the die pads without substantially covering the channel with solder. The manufacturing method further includes singulating the packages.

摘要翻译： 本文公开了一种制造半导体封装的方法，该半导体封装在引线焊盘上具有焊接位置，该焊盘抵达封装的边缘（非拉回引线）。 它包括将多个管芯封装在引线框架条上。 引线框架条包括多个封装位置，其还包括多个引线焊盘和管芯焊盘。 该方法还包括在附近的封装位置的引线焊盘之间形成通道，而不需要对封装进行分离。 该方法的另一步骤包括在焊盘，芯片焊盘或引线焊盘和裸片焊盘上布置焊料，而基本上不用焊料覆盖焊道。 制造方法还包括将包装分离。

公开(公告)号：US08154117B2

公开(公告)日：2012-04-10

申请号：US12347522

申请日：2008-12-31

申请人： Stefan W. Wiktor ,  Vladimir A. Muratov ,  Anthony L. Coyle ,  Bernhard P. Lange

发明人： Stefan W. Wiktor ,  Vladimir A. Muratov ,  Anthony L. Coyle ,  Bernhard P. Lange

IPC分类号： H01L23/488

CPC分类号： H01L24/06 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated circuit (IC) includes a substrate having a semiconducting surface, a first array of devices on and in the semiconducting surface including first and second coacting current conducting nodes, a plurality of layers disposed on the substrate and including at a electrically conductive layers and dielectric layer, and a plurality of bump pads on or in the top surface of the dielectric layers. In the IC, the electrically conductive layers define electrical traces, where a first portion of the electrical traces contact a first portion of the bump pads exclusively to a portion of the first coacting current conducting nodes, where a second portion of the electrical traces contact a second portion of the bump pads exclusively to a portion of the second coacting current conducting nodes, and where the electrical traces are electrically isolated from one another by the dielectric layers.

摘要翻译： 集成电路（IC）包括具有半导体表面的衬底，在半导体表面上和半导体表面中的第一阵列的器件，包括第一和第二共同电流导电节点，多个层，设置在衬底上并且包括导电层和 电介质层，以及介电层顶表面上或其中的多个凸块焊盘。 在IC中，导电层限定电迹线，其中电迹线的第一部分将凸点焊盘的第一部分独占地与第一共同电流传导节点的一部分接触，其中电迹线的第二部分接触 凸块的第二部分专用于第二共同电流传导节点的一部分，并且其中电迹线通过电介质层彼此电隔离。

公开(公告)号：US07635613B2

公开(公告)日：2009-12-22

申请号：US11168000

申请日：2005-06-27

申请人： Bernhard P. Lange ,  Steven A. Kummerl

发明人： Bernhard P. Lange ,  Steven A. Kummerl

IPC分类号： H01L23/495

CPC分类号： H01L23/4334 ,  H01L21/565 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device comprising a leadframe (903), which has first (903a) and second (903b) surfaces, a planar pad (910) of a certain size, and a plurality of non-coplanar members (913) adjoining the pad. The device further has a heat spreader (920) with first (920a) and second (920b) surfaces, a planar pad of a size matching the leadframe pad size, and contours (922), into which the leadframe members are inserted so that the first spreader pad surface touches the second leadframe pad surface across the pad size. A semiconductor chip (904) is mounted on the first leadframe pad surface. Encapsulation material (930), preferably molding compound, covers the chip, but leaves the second spreader surface uncovered.

摘要翻译： 一种半导体器件，包括具有第一（903a）和第二（903b）表面的引线框架（903），具有一定尺寸的平面焊盘（910）和与所述焊盘相邻的多个非共面构件（913）。 该装置还具有带有第一（920a）和第二（920b）表面的散热器（920），具有与引线框垫尺寸相匹配的尺寸的平面焊盘和轮廓（922），引线框架构件插入其中，使得 第一扩散器焊盘表面穿过焊盘尺寸接触第二引线框焊盘表面。 半导体芯片（904）安装在第一引线框焊盘表面上。 封装材料（930），优选模塑料覆盖芯片，但是将第二撒布机表面露出。

公开(公告)号：US07578422B2

公开(公告)日：2009-08-25

申请号：US11733870

申请日：2007-04-11

申请人： Bernhard P. Lange ,  Steven A. Kummerl

发明人： Bernhard P. Lange ,  Steven A. Kummerl

IPC分类号： B23K1/06

CPC分类号： B23K20/005 ,  B23K20/004 ,  B23K20/106 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4847 ,  H01L2224/78313 ,  H01L2224/78318 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/2076 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A device (100) and method (200) for bonding a ribbon wire (104) to a workpiece (106) comprising feeding the ribbon wire through a passageway (116) of an ultrasonic bond capillary (102) and clamping the ribbon wire against an engagement surface (120) of the bond capillary via a clamping jaw (118) operably coupled to the bond capillary. The ribbon wire (104) is bonded to the workpiece (106) along a bonding surface (112) of the bond capillary (102) and penetrated, at least partially, between the bonding surface and the engagement surface (120) of the bond capillary by a cutting tool (124). The cutting tool (124) may comprise an elongate member (126) positioned between the bonding surface (112) and engagement surface (120), and may have a cutting blade (128) positioned at a distal end (130) thereof. The cutting tool (124) may further comprise a ring cutter (132), wherein the ribbon wire passes through a ring (134) having a cutting surface (138) defined about an inner diameter thereof.

摘要翻译： 一种用于将带状线（104）接合到工件（106）的装置（100）和方法（200），包括通过超声波接合毛细管（102）的通道（116）馈送带状线并将带状线夹紧 通过可操作地耦合到粘结毛细管的夹钳（118）将粘结毛细管的接合表面（120）。 带状线（104）沿粘结毛细管（102）的接合表面（112）结合到工件（106）上，并且至少部分地穿过接合表面和粘结毛细管的接合表面（120）之间 通过切割工具（124）。 切割工具（124）可以包括定位在接合表面（112）和接合表面（120）之间的细长构件（126），并且可以具有定位在其远端（130）处的切割刀片（128）。 切割工具（124）还可以包括环形切割器（132），其中，带状丝线穿过具有围绕其内径限定的切割表面（138）的环（134）。

公开(公告)号：US20080001264A1

公开(公告)日：2008-01-03

申请号：US11480801

申请日：2006-07-03

申请人： Bernhard P. Lange

发明人： Bernhard P. Lange

IPC分类号： H01L23/495

CPC分类号： H01L23/49582 ,  H01L21/4842 ,  H01L23/3142 ,  H01L23/49503 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48472 ,  H01L2224/48664 ,  H01L2224/48764 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/85464 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In a method and system for fabricating a leadframe (100), a thickness of bondable areas (150, 152 and 154) of the leadframe (100) is reduced. A plating finish (160) is applied to a surface of the leadframe (100), including the surface of the bondable areas (150, 152 and 154) to provide a smooth texture. A selective portion (102) of the surface is removed by grinding off the plating finish (160) on the selective portion (102) to provide a rough texture while substantially preserving the smooth texture on the bondable areas (150, 152 and 154). Removal of the plating finish (160) on the selective portion (102) causes the selective portion (102) to form the rough texture, compared to the smooth texture of the plating finish (160). The rough texture provides increased adhesion to a polymeric compound compared to an adhesion provided by the smooth texture. Bondability of the bondable areas (150, 152 and 154) is maintained by preserving the smooth texture of the plating finish (160).

摘要翻译： 在用于制造引线框架（100）的方法和系统中，引线框架（100）的可粘合区域（150,152和154）的厚度减小。 电镀终端（160）被施加到引线框架（100）的包括可粘合区域（150,152和154）的表面的表面，以提供光滑的纹理。 通过研磨选择部分（102）上的电镀光洁度（160）来去除表面的选择部分（102），以提供粗糙的纹理，同时基本上保持可粘合区域（150,152和154）上的光滑纹理。 与镀层（160）的光滑质地相比，去除选择部分（102）上的镀层（160）导致选择部分（102）形成粗糙的纹理。 与由光滑纹理提供的粘合相比，粗糙纹理提供对聚合物的增加的粘合性。 通过保持电镀光洁度（160）的光滑纹理来保持可粘合区域（150,152和154）的粘合性。