公开(公告)号：US20180040482A1

公开(公告)日：2018-02-08

申请号：US15594883

申请日：2017-05-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/772 ,  H01L21/306 ,  G11C16/04

CPC classification number: H01L21/28 ,  G11C16/0425 ,  H01L21/28273 ,  H01L21/30604 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/772

Abstract: A method of forming a memory device that includes forming a first insulation layer on a semiconductor substrate, forming a conductive material layer on the first insulation layer, forming an insulation block on the conductive material layer, forming an insulation spacer along a side surface of the insulation block and on the conductive material layer, etching the conductive material layer to form a block of the conductive material disposed directly under the insulation block and the insulation spacer, removing the insulation spacer, forming a second insulation layer having a first portion wrapping around an exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer over the substrate, and forming a conductive block insulated from the block of the conductive material by the second insulation layer and from the substrate by the first and second insulation layers.

公开(公告)号：US09810662B1

公开(公告)日：2017-11-07

申请号：US15406809

申请日：2017-01-16

Applicant: CHIP WIN TECHNOLOGY CO., LTD. ,  Chao-Ching Yu

Inventor： Chao-Ching Yu ,  Lin-Ta Chung ,  Hsi-Ying Yuan ,  Ke-Pan Liao

IPC: G01N27/414 ,  H01L21/76 ,  H01L29/772 ,  H01L29/00 ,  H01L21/70 ,  G01N27/00

CPC classification number: G01N27/4145 ,  B01L3/502707 ,  B01L3/502715 ,  B01L2200/027 ,  B01L2300/0636 ,  B01L2300/0645 ,  B01L2300/0816 ,  B01L2300/0887 ,  G01N27/00 ,  G01N33/48707 ,  H01L21/70 ,  H01L21/76 ,  H01L29/00 ,  H01L29/772

Abstract: The present invention provides a structure for integrating microfluidic devices and electrical biosensors, including: a substrate for carrying an electrical biosensor; a microfluidic channel layer for providing at least a fluid to flow; a cover member for the inflow and outflow of the at least a fluid, and an electrical biosensor, having a biosensing layer and mounted to the cover member in a flip-chip manner; wherein the fluid flows into an inlet, passes the electrical biosensor for sensing and flows out through a fluid outlet.

公开(公告)号：US09799750B2

公开(公告)日：2017-10-24

申请号：US13551107

申请日：2012-07-17

Applicant: Chun-Fai Cheng ,  Han-Ting Tsai ,  An-Shen Chang ,  Hui-Min Lin

Inventor： Chun-Fai Cheng ,  Han-Ting Tsai ,  An-Shen Chang ,  Hui-Min Lin

IPC: H01L29/772 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. An isolation structure is formed in a substrate and a gate stack is formed atop the isolation structure. A spacer is formed adjoining a sidewall of the gate stack and extends beyond an edge of the isolation structure. The disclosed method provides an improved method for protecting the isolation structure by using the spacer. The spacer can prevent the isolation structure from being damaged by chemicals, therefor, to enhance contact landing and upgrade the device performance.

公开(公告)号：US09786780B2

公开(公告)日：2017-10-10

申请号：US14312871

申请日：2014-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Hsien Huang ,  Yi-Fang Pai ,  Chien-Chang Su

IPC: H01L29/772 ,  H01L29/41 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/417 ,  H01L29/165

CPC classification number: H01L29/7833 ,  H01L21/02636 ,  H01L29/0692 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit includes a gate structure over a substrate. A silicon-containing material structure is in each of recesses that are adjacent to the gate structure. The silicon-containing material structure has a first region and a second region, the second region is closer to the gate structure than the first region, and the first region is thicker than the second region.

公开(公告)号：US09727123B1

公开(公告)日：2017-08-08

申请号：US15200538

申请日：2016-07-01

Applicant: Cypress Semiconductor Corporation

Inventor： Anup Nayak ,  Ramakrishna Venigalla

IPC: G06F9/00 ,  H01L29/76 ,  H01L29/772 ,  G06F1/32 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F1/3287 ,  G06F1/266 ,  G06F13/385 ,  G06F13/4072 ,  G06F13/4282 ,  G06F2213/0042 ,  Y02D10/14 ,  Y02D10/151

Abstract: Techniques for power Field Effect Transistor (power-FET) gate drivers are described herein. In an example embodiment, a device comprises a Universal Serial Bus (USB) subsystem that is disposed in a monolithic integrated circuit (IC). The USB subsystem comprises a gate-driver circuit configured to selectively control an external N-channel power-FET or an external P-channel power-FET.

公开(公告)号：US09725298B2

公开(公告)日：2017-08-08

申请号：US14988842

申请日：2016-01-06

Applicant: Robert Bosch GmbH

Inventor： Ando Feyh ,  Po-Jui Chen ,  Markus Ulm

IPC: H01L29/84 ,  H01L21/50 ,  B81C1/00 ,  B81B3/00 ,  B81B7/00 ,  H01L29/772 ,  H01L21/02 ,  H01L21/58

CPC classification number: B81B3/0021 ,  B81B2201/0221 ,  B81B2201/0228 ,  B81C1/00134 ,  B81C1/00246 ,  B81C2203/0771

Abstract: A method of fabricating a semiconductor device comprises forming a dielectric layer above a substrate, the dielectric layer including a fixed dielectric portion and a proof mass portion, forming a source region and a drain region in the substrate, forming a gate electrode in the proof mass portion, and releasing the proof mass portion, such that the proof mass portion is movable with respect to the fixed dielectric portion and the gate electrode is movable with the proof mass portion relative to the source region and the drain region.

公开(公告)号：US20170200790A1

公开(公告)日：2017-07-13

申请号：US15320253

申请日：2015-07-21

Applicant: FLOSFIA INC.

Inventor： Toshimi Hitora ,  Masaya Oda ,  Akio Takatsuka

IPC: H01L29/24 ,  H01L29/778 ,  H01L29/808 ,  H01L29/772 ,  H01L29/739 ,  H01L33/26 ,  H01L29/78 ,  H01L29/66 ,  H01L33/00 ,  H01L29/812 ,  H01L21/02 ,  C23C16/448 ,  C23C16/44 ,  C23C16/40 ,  H01L29/872

Abstract: A semiconductor film, a sheet like object, and a semiconductor device are provided that have inhibited semiconductor properties, particularly leakage current, and excellent withstand voltage and heat dissipation. A crystalline semiconductor film or a sheet like object includes a corundum structured oxide semiconductor as a major component, wherein the film has a film thickness of 1 μm or more. Particularly, the semiconductor film or the object includes a semiconductor component of oxide of one or more selected from gallium, indium, and aluminum as a major component. A semiconductor device has a semiconductor structure including the semiconductor film or the object.

公开(公告)号：US09698058B2

公开(公告)日：2017-07-04

申请号：US14924422

申请日：2015-10-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng Ching ,  Ka-Hing Fung ,  Chih-Sheng Chang ,  Zhiqiang Wu

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/772 ,  H01L27/088 ,  H01L27/12 ,  H01L29/66 ,  H01L21/02 ,  H01L21/84 ,  H01L29/165

CPC classification number: H01L21/823821 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7831 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7855

Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner.

公开(公告)号：US09583583B2

公开(公告)日：2017-02-28

申请号：US14969025

申请日：2015-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Seoul National University R&DB Foundation

Inventor： Min-Chul Sun ,  Byung-Gook Park

IPC: H01L31/072 ,  H01L29/423 ,  H01L29/06 ,  H01L27/088 ,  H01L29/772 ,  H01L21/8234 ,  H01L29/786 ,  H01L27/12 ,  B82Y99/00

CPC classification number: H01L21/823412 ,  B82Y99/00 ,  H01L21/02532 ,  H01L21/02647 ,  H01L21/3065 ,  H01L27/088 ,  H01L27/1222 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/772 ,  H01L29/7843 ,  H01L29/78651 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

Abstract: A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.

Abstract translation: 半导体器件具有形成在基板上的各个区域中的栅极全绕器件。 全门设备具有不同级别的纳米线。 第一区域中的栅极全周围器件的阈值电压基于相邻第二区域中的有源层的厚度。 第二区域中的有源层可以处于与第一区域中的纳米线基本相同的水平。 因此，第一区域中的纳米线可以具有基于第二区域中的有源层的厚度的厚度，或者厚度可以不同。 当包括多于一个活性层时，不同区域中的纳米线可以设置在不同的高度和/或可以具有不同的厚度。

公开(公告)号：US09576954B1

公开(公告)日：2017-02-21

申请号：US14862258

申请日：2015-09-23

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Sanjay C. Mehta ,  Balasubramanian S. Pranatharthiharan ,  Ruilong Xie

IPC: H01L27/092 ,  H01L29/772 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/4983 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76205 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a sacrificial gate material and a hard mask layer; forming a first gate spacer along a sidewall of the first dummy gate and a second gate spacer along a sidewall of the second dummy gate; performing an epitaxial growth process to form a source/drain on the substrate between the first and second dummy gates; disposing a conformal liner over the first and second dummy gates and the source/drain; disposing an oxide on the conformal liner between the first and second dummy gates; recessing the oxide to a level below the hard mask layers of the first and second dummy gates to form a recessed oxide; and depositing a spacer material over the recessed oxide between the first dummy gate and the second dummy gate.

Abstract translation: 在栅极之间填充沟槽的方法包括在衬底上形成第一和第二虚拟栅极，第一和第二伪栅极包括牺牲栅极材料和硬掩模层; 沿着第一伪栅极的侧壁形成第一栅极间隔物，沿着第二虚拟栅极的侧壁形成第二栅极间隔物; 执行外延生长工艺以在第一和第二虚拟栅极之间的衬底上形成源极/漏极; 在第一和第二伪栅极和源极/漏极上设置保形衬垫; 在第一和第二伪栅极之间的保形衬垫上设置氧化物; 将氧化物凹陷到低于第一和第二伪栅极的硬掩模层的水平以形成凹陷氧化物; 以及在第一伪栅极和第二虚拟栅极之间的凹陷氧化物上沉积间隔物材料。