公开(公告)号：US20240021480A1

公开(公告)日：2024-01-18

申请号：US17865109

申请日：2022-07-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Che CHIANG ,  Wei-Chih KAO

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L27/0886 ,  H01L21/823481

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a first dielectric fin and a second dielectric fin over a substrate, and the second dielectric fin is taller than the first dielectric fin. The method also includes forming a gate stack over the substrate, and the gate stack extends across the first dielectric fin and the second dielectric fin. The method further includes partially removing the gate stack such that an opening exposing the second dielectric fin is formed and forming an isolation structure in the opening.

公开(公告)号：US11876121B2

公开(公告)日：2024-01-16

申请号：US17871693

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Walid M. Hafez

IPC: H01L29/49 ,  H01L27/088 ,  H01L23/535 ,  H01L21/8234

CPC classification number: H01L29/4983 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0886

Abstract: Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.

公开(公告)号：US11876013B2

公开(公告)日：2024-01-16

申请号：US17501818

申请日：2021-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Yuan Ku ,  Chih-Ming Sun ,  Chun-Fai Cheng

IPC: H01L21/762 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76232 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/088 ,  H01L29/4011 ,  H01L29/785 ,  H01L21/823437 ,  H01L29/66795

Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

公开(公告)号：US11869811B2

公开(公告)日：2024-01-09

申请号：US17562802

申请日：2021-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Lee ,  Jeongyun Lee ,  Yongseok Lee ,  Bosoon Kim ,  Sangduk Park ,  Seungchul Oh ,  Youngmook Oh

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/08 ,  H01L21/8238

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0847 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823814 ,  H01L27/0886

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

公开(公告)号：US20230420545A1

公开(公告)日：2023-12-28

申请号：US18367292

申请日：2023-09-12

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Byron HO ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.

公开(公告)号：US11855223B2

公开(公告)日：2023-12-26

申请号：US17549827

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Leonard P. Guler ,  Dax M. Crum ,  Tahir Ghani

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7856 ,  H01L21/02603 ,  H01L21/823481 ,  H01L23/5226 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/42392 ,  H01L2029/7858

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

公开(公告)号：US11854688B2

公开(公告)日：2023-12-26

申请号：US16888264

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8238 ,  G16H40/20 ,  G16H40/63 ,  H04L9/40 ,  G06Q50/16 ,  G06Q10/20

CPC classification number: G16H40/20 ,  G06Q50/163 ,  G16H40/63 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823807 ,  H01L27/0886 ,  H01L29/66795 ,  H04L63/0876 ,  G06Q10/20 ,  H01L21/823821 ,  H01L29/66545

Abstract: Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride (HF) and ammonia (NH3).

公开(公告)号：US20230411216A1

公开(公告)日：2023-12-21

申请号：US18362163

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Wei Lee ,  Chien-Yuan Chen ,  Jo-Chun Hung ,  Yung-Hsiang Chan ,  Yu-Kuan Lin ,  Lien-Jung Hung

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/823431 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L21/823821 ,  H01L29/6681 ,  H01L29/7851 ,  H01L29/66742 ,  H01L21/823481 ,  H01L21/823412

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

公开(公告)号：US20230402454A1

公开(公告)日：2023-12-14

申请号：US18133977

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin Lee ,  Junhee Lim ,  Kangoh Yun ,  Sohyun Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/76232

Abstract: A semiconductor device includes a first isolation structure extending through an upper portion of a substrate and defining a first active region, a first gate structure on the substrate, and first source/drain regions at upper portions of the first active region adjacent to the first gate structure. The first isolation structure includes an upper isolation pattern structure and a lower isolation pattern. The upper isolation pattern structure includes a first isolation pattern and a second isolation pattern covering a sidewall of the first isolation pattern. The lower isolation pattern is formed under and contacting the upper isolation pattern structure, and a width of the lower isolation pattern is greater than a width of the upper isolation pattern structure.

公开(公告)号：US11842920B2

公开(公告)日：2023-12-12

申请号：US17353618

申请日：2021-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun Hao Liao ,  Chu Fu Chen ,  Chun-Wei Hsu ,  Chia-Cheng Pao

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/76 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/66477

Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.