公开(公告)号：US11329138B2

公开(公告)日：2022-05-10

申请号：US15943552

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Christopher Kenyon ,  Sridhar Govindaraju ,  Chia-Hong Jan ,  Mark Liu ,  Szuya S. Liao ,  Walid M. Hafez

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088

Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.

公开(公告)号：US20240329114A1

公开(公告)日：2024-10-03

申请号：US18128733

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Amit Paliwal ,  Xiao Wen ,  Dipto Thakurta ,  Manish Sharma ,  Daniel Murray

IPC: G01R31/28

CPC classification number: G01R31/2851

Abstract: An integrated circuit on a production die comprises a device under test (DUT) cell array formed in a fill region on the production die, the DUT cell array comprising a plurality of DUT transistor structures configured for voltage contrast (VC) detection of electrical opens on the production die. The DUT transistor structures comprise one or more vias that are not located on power lines or signal lines, such that the DUT transistor structures are not connected to each other or to the electrically functioning transistors. A guard ring buffer is formed at a transition between the active transistor region and the DUT cell array.

公开(公告)号：US11935892B2

公开(公告)日：2024-03-19

申请号：US17862305

申请日：2022-07-11

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Walid M. Hafez

IPC: H01L29/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L27/0924 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

公开(公告)号：US11444171B2

公开(公告)日：2022-09-13

申请号：US16294307

申请日：2019-03-06

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Walid M. Hafez

IPC: H01L29/49 ,  H01L27/088 ,  H01L23/535 ,  H01L21/8234

Abstract: Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.

公开(公告)号：US11605632B2

公开(公告)日：2023-03-14

申请号：US17529029

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Sridhar Govindaraju ,  Mark Liu ,  Szuya S. Liao ,  Chia-Hong Jan ,  Nick Lindert ,  Christopher Kenyon ,  Sairam Subramanian

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L23/528

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

公开(公告)号：US11563000B2

公开(公告)日：2023-01-24

申请号：US16830120

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Chia-Hong Jan

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: Gate endcap architectures having relatively short vertical stack, and methods of fabricating gate endcap architectures having relatively short vertical stack, are described. In an example, an integrated circuit structure includes a first semiconductor fin along a first direction. A second semiconductor fin is along the first direction. A trench isolation material is between the first semiconductor fin and the second semiconductor fin. The trench isolation material has an uppermost surface below a top of the first and second semiconductor fins. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin and is along the first direction. The gate endcap isolation structure is on the uppermost surface of the trench isolation material.

公开(公告)号：US20190304902A1

公开(公告)日：2019-10-03

申请号：US15940531

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Walid M. Hafez

IPC: H01L23/522 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768

Abstract: Integrated circuit structures including device terminal interconnect pillar structures, and fabrication techniques to form such structures. Following embodiments herein, a small transistor terminal interconnect footprint may be achieved by patterning recesses in a gate interconnect material and/or a source or drain interconnect material. A dielectric deposited over the gate interconnect material and/or source or drain interconnect material may be planarized to expose portions of the gate interconnect material and/or drain interconnect material that were protected from the recess patterning. An upper level interconnect structure, such as a conductive line or via, may contact the exposed portion of the gate and/or source or drain interconnect material.

公开(公告)号：US12199101B2

公开(公告)日：2025-01-14

申请号：US18410917

申请日：2024-01-11

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Walid M. Hafez

IPC: H01L29/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062

Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

公开(公告)号：US12013442B2

公开(公告)日：2024-06-18

申请号：US16147564

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Enlan Yuan ,  David Sanchez ,  Amit Paliwal ,  Manish Sharma ,  Sairam Subramanian ,  Sagar Suthram

IPC: H01L21/66 ,  G01R31/28 ,  G01R31/307 ,  G01R31/50 ,  H01L27/02

CPC classification number: G01R31/50 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/307 ,  H01L22/32 ,  H01L22/34

Abstract: Embodiments of the present disclosure relate to in-line detection of electrical fails on integrated circuits. One embodiment is an apparatus including a device region with integrated circuits and a test region for in-line failure detection of the integrated circuits using an in-line voltage contrast test, the apparatus comprising: a substrate including a first area for the device region and a second different area for the test region; metal layers formed over both areas; wherein the integrated circuits are formed from first sections of the layers; and wherein a second section of an upper metal layer of the layers is segmented into test segments, each test segment to exhibit a predefined response during the in-line voltage contrast test depending on whether the test segment is shorted, or not, to the substrate and/or the second section of a gate layer of the layer. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US20220122911A1

公开(公告)日：2022-04-21

申请号：US17562925

申请日：2021-12-27

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Walid M. Hafez

IPC: H01L23/522 ,  H01L27/088 ,  H01L21/768 ,  H01L21/8234

Abstract: Integrated circuit structures including device terminal interconnect pillar structures, and fabrication techniques to form such structures. Following embodiments herein, a small transistor terminal interconnect footprint may be achieved by patterning recesses in a gate interconnect material and/or a source or drain interconnect material. A dielectric deposited over the gate interconnect material and/or source or drain interconnect material may be planarized to expose portions of the gate interconnect material and/or drain interconnect material that were protected from the recess patterning. An upper level interconnect structure, such as a conductive line or via, may contact the exposed portion of the gate and/or source or drain interconnect material.