公开(公告)号：US20130307144A1

公开(公告)日：2013-11-21

申请号：US13544746

申请日：2012-07-09

Applicant: Chen-Hua YU ,  Da-Yuan SHIH ,  Chih-Hang TUNG

Inventor： Chen-Hua YU ,  Da-Yuan SHIH ,  Chih-Hang TUNG

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/48 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/488 ,  H01L23/52 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/11466 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/1184 ,  H01L2224/13005 ,  H01L2224/13019 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13618 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13669 ,  H01L2224/13673 ,  H01L2224/13676 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/2919 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/81205 ,  H01L2224/8183 ,  H01L2224/81895 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/206 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A three dimensional (3D) chip stack includes a first chip bonded to a second chip. The first chip includes a first bump structure overlying the first substrate, and the second chip includes a second bump structure overlying the second substrate. The first bump structure is attached to the second bump structure, and a joining region is formed between the first bump structure and the second bump structure. The joining region is a solderless region which includes a noble metal.

Abstract translation: 三维（3D）芯片堆叠包括结合到第二芯片的第一芯片。 第一芯片包括覆盖第一基板的第一凸块结构，并且第二芯片包括覆盖第二基板的第二凸块结构。 第一凸块结构附接到第二凸块结构，并且在第一凸块结构和第二凸块结构之间形成接合区域。 接合区域是包括贵金属的无焊区域。

公开(公告)号：US20130068373A1

公开(公告)日：2013-03-21

申请号：US13604687

申请日：2012-09-06

Applicant: Michael SCHÄFER ,  Wolfgang SCHMITT ,  Albert HEILMANN ,  Jens NACHREINER

Inventor： Michael SCHÄFER ,  Wolfgang SCHMITT ,  Albert HEILMANN ,  Jens NACHREINER

IPC: C09J11/06 ,  B29C65/48

CPC classification number: B22F1/0074 ,  B22F7/08 ,  B23K35/025 ,  B23K35/3006 ,  B23K35/3618 ,  H01B1/22 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/2732 ,  H01L2224/2741 ,  H01L2224/27418 ,  H01L2224/27422 ,  H01L2224/27848 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/83192 ,  H01L2224/83418 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8384 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/01327 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A paste may be used to connect at least one electronic component to at least one substrate through contact regions, wherein at least one of the contact regions contains a non-noble metal. The paste contains (a) metal particles, (b) at least one activator that bears at least two carboxylic acid units in the molecule, and (c) a dispersion medium. A method for connecting at least one electronic component to at least one substrate through the contact regions includes steps of providing a substrate having a first contact region and an electronic component having a second contact region; providing the above paste; generating a structure, wherein the first contact region of the substrate contacts the second contact region of the electronic component through the paste; and sintering the structure while producing a module including at least the substrate and the electronic component connected to each other through the sintered paste.

Abstract translation: 糊剂可以用于通过接触区域将至少一个电子部件连接到至少一个基板，其中至少一个接触区域包含非贵金属。 糊状物包含（a）金属颗粒，（b）至少一种在分子中至少含有两个羧酸单元的活化剂，和（c）分散介质。 通过接触区域将至少一个电子部件连接到至少一个基板的方法包括提供具有第一接触区域的基板和具有第二接触区域的电子部件的步骤; 提供上述糊状物; 产生结构，其中所述基板的所述第一接触区域通过所述浆料接触所述电子部件的所述第二接触区域; 以及烧结所述结构体，同时制造至少包括通过所述烧结膏彼此连接的所述基板和所述电子部件的模块。

公开(公告)号：US20120217650A1

公开(公告)日：2012-08-30

申请号：US13403338

申请日：2012-02-23

Applicant: Hideo IMAI

Inventor： Hideo IMAI

IPC: H01L23/538

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/562 ,  H01L25/0657 ,  H01L25/074 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13144 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81895 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01327 ,  H01L2924/00

Abstract: A first substrate with a penetration electrode formed thereon is stacked on a second substrate with a protruding electrode formed thereon. The penetration electrode has a recessed portion. The substrates are stacked with the protruding electrode entered in the recessed portion. A distal width of the protruding electrode is smaller than an opening width of the recessed portion.

Abstract translation: 在其上形成有穿透电极的第一基板层叠在其上形成有突出电极的第二基板上。 穿透电极具有凹部。 基板被突出电极堆叠在凹入部分中。 突出电极的前端宽度小于凹部的开口宽度。

公开(公告)号：US20120181688A1

公开(公告)日：2012-07-19

申请号：US13355311

申请日：2012-01-20

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H01L23/498

CPC classification number: H01L24/00 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13171 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/3473 ,  H05K3/4007 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/099 ,  H05K2203/054 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

Abstract: A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

Abstract translation: 提供一种具有导电结构的封装基板，包括其表面上具有至少一个导电焊盘的基板主体，设置在导电焊盘上的应力缓冲金属层，应力缓冲金属层的厚度为1-20μm， 防焊层设置在基板主体上并且在其中具有至少一个开口，用于相应地暴露应力缓冲金属层的顶表面的一部分，设置在应力缓冲金属层的表面的中心部分上的金属柱，以及 焊料凸块覆盖金属柱的表面。 因此，通过使用应力缓冲金属层来释放热应力，并且使用金属柱和焊料凸块来增加导电结构的高度，提供了高度可靠的导电结构。

公开(公告)号：US08183683B1

公开(公告)日：2012-05-22

申请号：US12549068

申请日：2009-08-27

Applicant: Joon Su Kim ,  Jung Soo Park ,  Tae Kyung Hwang

Inventor： Joon Su Kim ,  Jung Soo Park ,  Tae Kyung Hwang

IPC: H01L23/488

CPC classification number: H01L24/05 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/02163 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05578 ,  H01L2224/05601 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48618 ,  H01L2224/48623 ,  H01L2224/48624 ,  H01L2224/48801 ,  H01L2224/48818 ,  H01L2224/48823 ,  H01L2224/48838 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01048 ,  H01L2924/01004 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2224/48638

Abstract: A semiconductor device is provided. The semiconductor device comprises a semiconductor die having bond pads, each of which consists of a first bond pad made of a material whose ionization tendency is relatively low and a second bond pad made of a material whose ionization tendency is relatively high. The second bond pads function as sacrificial anodes to prevent the occurrence of galvanic corrosion at the interfaces between the first bond pads and conductive wires. In an embodiment, the upper surfaces of the second bond pads are marked instead of those of the first bond pads, which reduces the number of defects in the first bond pads. A method for fabricating the semiconductor device is also provided.

Abstract translation: 提供半导体器件。 半导体器件包括具有接合焊盘的半导体管芯，每个半导体管芯由电离倾向相对较低的材料制成的第一接合焊盘和由电离倾向相对较高的材料制成的第二接合焊盘构成。 第二接合焊盘用作牺牲阳极，以防止在第一接合焊盘和导电线之间的界面处发生电偶腐蚀。 在一个实施例中，标记第二接合焊盘的上表面而不是第一接合焊盘的上表面，这减少了第一接合焊盘中的缺陷数量。 还提供了一种用于制造半导体器件的方法。

公开(公告)号：US07833881B2

公开(公告)日：2010-11-16

申请号：US11681648

申请日：2007-03-02

Applicant: Warren M. Farnworth

Inventor： Warren M. Farnworth

IPC: H01L21/00

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3157 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/013 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Packaged semiconductor components and methods for manufacturing packaged semiconductor components. In one embodiment a semiconductor component comprises a die having a semiconductor substrate and an integrated circuit. The substrate has a first side, a second side, a sidewall between the first and second sides, a first indentation at the sidewall around a periphery of the first side, and a second indentation at the sidewall around a periphery of the second side. The component can further include a first exterior cover at the first side and a second exterior cover at the second side. The first exterior cover has a first extension in the first indentation, and the second exterior cover has a second extension in the second indentation. The first and second extensions are spaced apart from each other by an exposed portion of the sidewall.

Abstract translation: 封装半导体元件和制造封装半导体元件的方法。 在一个实施例中，半导体部件包括具有半导体衬底和集成电路的管芯。 衬底具有第一侧面，第二侧面，第一侧面和第二侧面之间的侧壁，围绕第一侧边缘的侧壁处的第一凹陷和围绕第二侧边缘的侧壁处的第二凹槽。 该部件还可以包括在第一侧的第一外部盖和在第二侧的第二外部盖。 第一外盖在第一压痕中具有第一延伸部，第二外盖在第二压痕中具有第二延伸部。 第一和第二延伸部通过侧壁的暴露部分彼此间隔开。

公开(公告)号：US20100163292A1

公开(公告)日：2010-07-01

申请号：US12483261

申请日：2009-06-12

Applicant: Tsung-Fu Tsai ,  Chau-Jie Zhan ,  Jing-Yao Chang ,  Tao-Chih Chang

Inventor： Tsung-Fu Tsai ,  Chau-Jie Zhan ,  Jing-Yao Chang ,  Tao-Chih Chang

IPC: H01R12/04

CPC classification number: H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05572 ,  H01L2224/05576 ,  H01L2224/05578 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/13116 ,  H01L2224/16145 ,  H01L2224/81191 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Abstract translation: 提供了一种包括载体，包括至少底部凸点冶金（UBM）层和至少一个导电凸块的衬底。 衬底具有导电结构，并且至少与导电结构连接的焊盘。 与导电结构连接的焊盘的区域是信号源区域。 UBM层设置在焊盘上并且包括第一导电图案和第二导电图案。 第二导电图案的侧壁直接连接到第一导电图案的侧壁，并且第二导电图案靠近信号源区域设置。 第二导电图案的导电性小于第一导电图案的导电率。 导电凸块设置在UBM层上。

公开(公告)号：US20080290528A1

公开(公告)日：2008-11-27

申请号：US11838665

申请日：2007-08-14

Applicant: Shih-Ping HSU

Inventor： Shih-Ping HSU

IPC: H01L23/48

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L2224/05001 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05085 ,  H01L2224/052 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/0562 ,  H01L2224/05623 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2224/05099 ,  H01L2924/013

Abstract: A semiconductor package substrate having electrical connecting pads includes: a substrate body having a plurality of electrical connecting pads formed on surface thereof, and a plurality of protruding lumps or concave areas of any geometric shape respectively formed on surfaces of the electrical connecting pads for increasing contact surfaces of the electrical connecting pads, thereby preventing detaching of conductive elements from surfaces of the electrical connecting pads caused by poor bonding force.

Abstract translation: 具有电连接焊盘的半导体封装基板包括：具有形成在其表面上的多个电连接焊盘的基板主体，以及分别形成在电连接焊盘的表面上的多个突起的块状或任何几何形状的凹入区域，用于增加接触 电连接焊盘的表面，从而防止导电元件从由不良粘合力引起的电连接焊盘的表面分离。

公开(公告)号：US20080213976A1

公开(公告)日：2008-09-04

申请号：US11681648

申请日：2007-03-02

Applicant: Warren M. Farnworth

Inventor： Warren M. Farnworth

IPC: H01L21/00

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3157 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/013 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Packaged semiconductor components and methods for manufacturing packaged semiconductor components. In one embodiment a semiconductor component comprises a die having a semiconductor substrate and an integrated circuit. The substrate has a first side, a second side, a sidewall between the first and second sides, a first indentation at the sidewall around a periphery of the first side, and a second indentation at the sidewall around a periphery of the second side. The component can further include a first exterior cover at the first side and a second exterior cover at the second side. The first exterior cover has a first extension in the first indentation, and the second exterior cover has a second extension in the second indentation. The first and second extensions are spaced apart from each other by an exposed portion of the sidewall.

Abstract translation: 封装半导体元件和制造封装半导体元件的方法。 在一个实施例中，半导体部件包括具有半导体衬底和集成电路的管芯。 衬底具有第一侧面，第二侧面，第一侧面和第二侧面之间的侧壁，围绕第一侧边缘的侧壁处的第一凹陷和围绕第二侧边缘的侧壁处的第二凹槽。 该部件还可以包括在第一侧的第一外部盖和在第二侧的第二外部盖。 第一外盖在第一压痕中具有第一延伸部，第二外盖在第二压痕中具有第二延伸部。 第一和第二延伸部通过侧壁的暴露部分彼此间隔开。

公开(公告)号：US20070108562A1

公开(公告)日：2007-05-17

申请号：US11616852

申请日：2006-12-27

Applicant: Young-Hee SONG ,  Il-Heung Choi ,  Jeong-Jin Kim ,  Hae-Jeong Sohn ,  Chung-Woo Lee

Inventor： Young-Hee SONG ,  Il-Heung Choi ,  Jeong-Jin Kim ,  Hae-Jeong Sohn ,  Chung-Woo Lee

IPC: H01L23/495

CPC classification number: H01L24/06 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49575 ,  H01L23/525 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05116 ,  H01L2224/05118 ,  H01L2224/05155 ,  H01L2224/0516 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05669 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48463 ,  H01L2224/48471 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/45099

Abstract: A semiconductor package includes a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern, The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region.

Abstract translation: 半导体封装包括具有形成在单元区域和彼此相邻的外围电路区域的集成电路的半导体衬底。 在半导体衬底上形成接合焊盘布线图形。 衬垫重排图案电连接到接合焊盘布线图案。衬垫重排图案包括设置在单元区域的至少一部分上的接合焊盘。