公开(公告)号：US08610006B2

公开(公告)日：2013-12-17

申请号：US12604907

申请日：2009-10-23

Applicant: Shih-Ping Hsu ,  Kun-Chen Tsai ,  Micallaef Ivan

Inventor： Shih-Ping Hsu ,  Kun-Chen Tsai ,  Micallaef Ivan

IPC: H01L23/28

CPC classification number: H05K9/0084 ,  B81B7/0061 ,  B81B7/0064 ,  B81B2201/0257 ,  H04R19/005

Abstract: A lid for a micro-electro-mechanical device and a method for fabricating the same are provided. The lid includes a board with opposite first and second surfaces and a first conductor layer. The first surface has a first metal layer thereon. The first metal layer and the board have a recess formed therein. The recess has a bottom surface and a side surface adjacent thereto. The first conductor layer is formed on the first metal layer and the bottom and side surfaces of the recess. The shielding effect of the side surface of the board is enhanced because of the recess integral to the board, the homogeneous bottom and side surfaces of the recess, and the first conductor layer covering the first metal layer, the bottom and side surfaces of the recess.

Abstract translation: 提供了一种微机电装置用盖及其制造方法。 盖子包括具有相对的第一和第二表面的板和第一导体层。 第一表面上具有第一金属层。 第一金属层和板具有形成在其中的凹部。 凹部具有底表面和与其相邻的侧表面。 第一导体层形成在第一金属层和凹部的底部和侧表面上。 板的侧面的屏蔽效果由于与板的整体凹部，凹部的均匀的底部和侧表面以及覆盖第一金属层的第一导体层，凹部的底部和侧表面而增强 。

公开(公告)号：US08531021B2

公开(公告)日：2013-09-10

申请号：US13160874

申请日：2011-06-15

Applicant: Chu-Chin Hu ,  Shih-Ping Hsu ,  Yi-Ju Chen

Inventor： Chu-Chin Hu ,  Shih-Ping Hsu ,  Yi-Ju Chen

IPC: H01L23/02

CPC classification number: H01L21/56 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L25/105 ,  H01L25/162 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A package stack device includes a first package structure having a plurality of first metal posts and a first electronic element disposed on a surface thereof, a second package structure having a plurality of second metal posts and a second electronic element disposed on opposite surfaces thereof, and an encapsulant formed between the first and second package structures for encapsulating the first electronic element. By connecting the first and second metal posts, the second package structure is stacked on the first package structure with the support of the metal posts and the encapsulant filling the gap therebetween so as to prevent warpage of the substrate.

Abstract translation: 包装堆叠装置包括具有多个第一金属柱和设置在其表面上的第一电子元件的第一封装结构，具有多个第二金属柱的第二封装结构和设置在其相对表面上的第二电子元件， 形成在第一和第二封装结构之间用于封装第一电子元件的密封剂。 通过连接第一和第二金属柱，第二封装结构被堆叠在第一封装结构上，金属柱的支撑件和密封剂填充其间的间隙，以防止基板翘曲。

公开(公告)号：US08101866B2

公开(公告)日：2012-01-24

申请号：US12175348

申请日：2008-07-17

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H01R9/00

CPC classification number: H05K3/3473 ,  H01L23/498 ,  H01L23/49816 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13565 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/099 ,  H05K2203/054 ,  H01L2224/05552

Abstract: A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

Abstract translation: 提供一种具有导电结构的封装基板，包括：具有在其表面上至少有一个导电焊盘的基板主体，设置在导电焊盘上的应力缓冲金属层，设置在基板主体上的阻焊层，并具有至少一个开口 用于相应地暴露应力缓冲金属层的顶表面的一部分，设置在应力缓冲金属层的表面的中心部分上的金属柱和覆盖金属柱的表面的焊料凸块。 因此，通过使用应力缓冲金属层来释放热应力，并且使用金属柱和焊料凸块来增加导电结构的高度，提供了高度可靠的导电结构。

公开(公告)号：US20110097851A1

公开(公告)日：2011-04-28

申请号：US12909222

申请日：2010-10-21

Applicant: Shih- Ping Hsu

Inventor： Shih- Ping Hsu

IPC: H01L21/302

CPC classification number: H01L21/561 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method fabricates a packaging structure, including cutting a complete panel of packaging substrates with a large area into a plurality of packaging substrate blocks each having a plurality of packaging substrate units; mounting a semiconductor chip on each of the packaging substrate units and securing the semiconductor chip to the packaging substrate unit with a molding material, to form a plurality of packaging structure blocks each having a plurality of packaging structure units; and cutting the packaging structure block into a plurality of packaging structure units. Accordingly, each of the packaging structure unit has a moderate area, the alignment difference between the packaging structure units in each of the packaging structure blocks can be reduced, and the semiconductor chips for all the packaging substrate units in each of the packaging substrate blocks can be packaged at one time. Therefore, the yield is increased and the overall cost is reduced.

Abstract translation: 一种制造包装结构的方法，包括将具有大面积的完整的包装衬底面板切割成多个包装衬底块，每个封装衬底块具有多个封装衬底单元; 将半导体芯片安装在每个封装基板单元上，并用成型材料将半导体芯片固定到封装基板单元，以形成多个封装结构块，每个封装结构块具有多个封装结构单元; 以及将所述包装结构块切割成多个包装结构单元。 因此，每个包装结构单元具有中等面积，可以减少每个包装结构块中的包装结构单元之间的对准差，并且用于每个包装基板块中的所有包装基板单元的半导体芯片可以 一次包装。 因此，产量提高，整体成本降低。

公开(公告)号：US20110042128A1

公开(公告)日：2011-02-24

申请号：US12858759

申请日：2010-08-18

Applicant: Shih- Ping HSU

Inventor： Shih- Ping HSU

IPC: H05K1/09 ,  H01L21/768 ,  H05K1/11

CPC classification number: H05K3/4007 ,  H01L2924/0002 ,  H05K3/205 ,  H05K3/3473 ,  H05K3/4682 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/10984 ,  Y10T29/49147 ,  H01L2924/00

Abstract: A coreless packaging substrate includes: a substrate body including an auxiliary dielectric layer having opposing first and second surfaces, an inner wiring formed on the second surface, and a built-up structure formed on both the second surface of the auxiliary dielectric layer and the inner wiring; and a plurality of conductive bumps including metal pillars having opposing first and second ends and a solder layer formed on the first end, wherein the second ends of the metal pillars are disposed in the auxiliary dielectric layer and electrically connecting with the inner wiring, and the first ends of the metal pillars with the solder layer protrude from the first surface of the auxiliary dielectric layer, thereby achieving ultra-fine pitch and even-height conductive bumps. A method for fabricating the coreless packaging substrate as described above is further provided.

Abstract translation: 无芯封装基板包括：基板主体，包括具有相对的第一和第二表面的辅助介电层，形成在第二表面上的内部布线，以及形成在辅助介电层的第二表面和内部 接线; 以及多个导电凸块，其包括具有相对的第一和第二端的金属柱和形成在第一端上的焊料层，其中金属柱的第二端设置在辅助介电层中并与内部布线电连接， 具有焊料层的金属柱的第一端从辅助介电层的第一表面突出，从而实现超细间距和均匀高度的导电凸块。 进一步提供如上所述的无芯封装基板的制造方法。

公开(公告)号：US07656040B2

公开(公告)日：2010-02-02

申请号：US11756403

申请日：2007-05-31

Applicant: Shih-Ping Hsu ,  Chung-Cheng Lien ,  Chia-Wei Chang

Inventor： Shih-Ping Hsu ,  Chung-Cheng Lien ,  Chia-Wei Chang

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/19041 ,  H05K1/186 ,  H05K3/323 ,  H05K3/4602 ,  H05K3/4614 ,  H05K2201/09536 ,  H05K2203/061 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stack structure of circuit boards embedded with semiconductor components therein is proposed, which includes at least two semiconductor components embedded circuit boards, a plurality of conductive bumps, and at least one adhesive layer. The circuit boards are each formed with a circuit layer having a plurality of electrical connection pads. The conductive bumps are formed on the electrical connection pads of at least one of the circuit boards. The adhesive layer is formed between the circuit boards such that a portion of the adhesive layer between the conductive bumps and the electrical connection pads, or between the opposing conductive bumps, forms a conductive channel and thereby forms an electrical connection between the circuit boards.

Abstract translation: 提出了嵌入其中的半导体部件的电路板的堆叠结构，其包括至少两个半导体部件嵌入式电路板，多个导电凸块和至少一个粘合剂层。 电路板各自形成有具有多个电连接焊盘的电路层。 导电凸块形成在至少一个电路板的电连接焊盘上。 粘合剂层形成在电路板之间，使得导电凸块和电连接焊盘之间或相对的导电凸块之间的粘合剂层的一部分形成导电通道，从而在电路板之间形成电连接。

公开(公告)号：US07639473B2

公开(公告)日：2009-12-29

申请号：US11925590

申请日：2007-10-26

Applicant: Shih-Ping Hsu ,  Kan-Jung Chia

Inventor： Shih-Ping Hsu ,  Kan-Jung Chia

IPC: F23Q3/00

CPC classification number: H05K1/185 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24227 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K1/162 ,  H05K3/429 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/10674 ,  H05K2203/0315 ,  H01L2924/00

Abstract: A circuit board structure with embedded electronic components includes: a carrier board having an adhesive layer with two surfaces formed with first and second metal oxide layers covered by first and second metal layers and having at least one through hole; at least one semiconductor chip received in the through hole of the carrier board; an adhesive material filling a gap between the through hole and the semiconductor chip so as to secure the semiconductor chip in position to the through hole; a high dielectric material layer formed outwardly on the second metal layer; and at least one electrode board formed outwardly on the high dielectric material layer such that a capacitance component is formed with the second metal layer, high dielectric material layer, and electrode board. Accordingly, the capacitance component is integrated into the circuit board structure.

Abstract translation: 具有嵌入式电子元件的电路板结构包括：具有粘合剂层的载体板，其具有形成有由第一和第二金属层覆盖并且具有至少一个通孔的第一和第二金属氧化物层的两个表面; 至少一个半导体芯片容纳在载板的通孔中; 填充通孔和半导体芯片之间的间隙的粘合材料，以将半导体芯片固定在通孔的适当位置; 在第二金属层上向外形成的高介电材料层; 以及至少一个在高电介质材料层上向外形成的电极板，使得电容元件形成有第二金属层，高介电材料层和电极板。 因此，电容分量被集成到电路板结构中。

公开(公告)号：US20090294993A1

公开(公告)日：2009-12-03

申请号：US12153914

申请日：2008-05-28

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H01L23/52

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K3/285 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/0195 ,  H01L2924/00

Abstract: A packaging substrate structure is disclosed, which comprises a dielectric material with Young's Modulus less than 1 Gpa and moisture absorption ratio less than 1.0% in a solder mask, an outer dielectric layer or the combination. The package substrate structure improves the stability and the integration of the product.

Abstract translation: 公开了一种包装衬底结构，其包括在焊料掩模，外部电介质层或组合中具有小于1Gpa的杨氏模量和小于1.0％的吸湿率的介电材料。 封装衬底结构提高了产品的稳定性和集成度。

公开(公告)号：US07614146B2

公开(公告)日：2009-11-10

申请号：US11867660

申请日：2007-10-04

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H05K3/42

CPC classification number: H05K3/427 ,  H05K1/116 ,  H05K3/108 ,  H05K3/426 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2203/0353 ,  Y10T29/49123 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The present invention provides a circuit board structure and a method of fabricating circuit board structure the same, the circuit board structure consisting of a carrier board having a first surface and an opposed second surface, the carrier board being formed with at least one through hole penetrating the first and second surfaces; a conductive pillar formed in the through hole by electroplating; and a first circuit layer and a second circuit layer respectively formed on the first and second surfaces of the carrier board, the first and second circuit layers being electrically connected to the two end portions of the conductive pillar, thereby reducing spacing between adjacent conductive pillars of the carrier board and achieving high density circuit layout.

Abstract translation: 本发明提供一种电路板结构及其制造方法，所述电路板结构由具有第一表面和相对的第二表面的载体板组成，所述载体板形成有至少一个穿透孔 第一和第二表面; 通过电镀形成在通孔中的导电柱; 以及分别形成在所述载板的所述第一和第二表面上的第一电路层和第二电路层，所述第一和第二电路层电连接到所述导电柱的两个端部，由此减小相邻导电柱之间的间隔 承载板实现高密度电路布局。

公开(公告)号：US20090168380A1

公开(公告)日：2009-07-02

申请号：US12340445

申请日：2008-12-19

Applicant: Shih-Ping Hsu ,  Kan-Jung Chia

Inventor： Shih-Ping Hsu ,  Kan-Jung Chia

IPC: H05K1/18

CPC classification number: H05K1/185 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/18162 ,  H05K3/4644 ,  H05K2201/10674 ,  H05K2203/072 ,  H05K2203/1469

Abstract: A package substrate embedded with a semiconductor component is provided. A semiconductor chip is received in a cavity of a substrate body, and has electrode pads on an active surface thereof. A passivation layer is disposed on the active surface and has openings for exposing the electrode pads. An electroless plating metal layer, a first sputtering metal layer and a second sputtering metal layer are sequentially formed on the electrode pads, the openings of the passivation layer and the passivation layer surface around the openings. Contact pads are formed on the second sputtering metal layer. A first dielectric layer is disposed on the substrate body and the passivation layer. A first circuit layer is formed on the first dielectric layer. First conductive vias are formed in the first dielectric layer and electrically connected to the contact pads. The first circuit layer is electrically connected to the first conductive vias.

Abstract translation: 提供了嵌入半导体部件的封装基板。 半导体芯片被接收在基板主体的空腔中，并且在其有效表面上具有电极焊盘。 钝化层设置在有源表面上并具有用于暴露电极焊盘的开口。 在电极焊盘，钝化层的开口和开口周围的钝化层表面上依次形成化学镀金属层，第一溅射金属层和第二溅射金属层。 接触焊盘形成在第二溅射金属层上。 第一电介质层设置在衬底主体和钝化层上。 在第一电介质层上形成第一电路层。 第一导电通孔形成在第一电介质层中并电连接到接触焊盘。 第一电路层电连接到第一导电通孔。