公开(公告)号：US20230163127A1

公开(公告)日：2023-05-25

申请号：US17455941

申请日：2021-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Julien Frougier ,  Chen Zhang ,  ZUOGUANG LIU ,  Ruilong Xie ,  Alexander Reznicek

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/66742

Abstract: A semiconductor device includes a lower nano device that includes a plurality of stacked first nano sheets, where the first nano sheets are spaced apart from each other a first distance. An upper nano device that includes a plurality of stacked second nano sheets, where the second nano sheets are spaced apart from each other a second distance, where the second distance is larger than the first distance.

公开(公告)号：US11659703B2

公开(公告)日：2023-05-23

申请号：US17187068

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jhon Jhy Liaw

IPC: H01L27/11 ,  H01L23/528 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  G11C11/419

CPC classification number: H01L27/1108 ,  G11C11/419 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/5286 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor structure includes a substrate and first SRAM cells and second SRAM cells. Each first SRAM cell includes two first p-type FinFET and four first n-type FinFET. Each first p-type and n-type FinFET includes a channel in a single semiconductor fin. The first SRAM cells are arranged with a first X-pitch and a first Y-pitch. Each second SRAM cell includes two second p-type FinFET and four second n-type FinFET. Each second p-type FinFET includes a channel in a single semiconductor fin. Each second n-type FinFET includes a channel in multiple semiconductor fins. The second SRAM cells are arranged with a second X-pitch and a second Y-pitch. The source/drain regions of the first p-type FinFET have a higher boron dopant concentration than the source/drain regions of the second p-type FinFET. A ratio of the second X-pitch to the first X-pitch is within a range of 1.1 to 1.5.

公开(公告)号：US20190252268A1

公开(公告)日：2019-08-15

申请号：US15897204

申请日：2018-02-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chanro Park ,  Laertis Economikos ,  Andrew M. Greene ,  Siva Kanakasabapathy ,  John R. Sporre

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L21/823864 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545

Abstract: Gate isolation methods and structures leverage the formation of a sidewall spacer layer within a recess formed in an organic planarization layer. The spacer layer enables precise alignment of the cut region of a sacrificial gate, which may be backfilled with an isolation layer. By forming the isolation layer after a reliability anneal of the gate dielectric and after formation of a first work function metal layer, both the desired critical dimension (CD) and alignment of the isolation layer can be achieved.

公开(公告)号：US20190245060A1

公开(公告)日：2019-08-08

申请号：US16386202

申请日：2019-04-16

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Byron HO ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7854 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.

公开(公告)号：US20190198500A1

公开(公告)日：2019-06-27

申请号：US16293853

申请日：2019-03-06

Applicant: International Business Machines Corporation

Inventor： RUQIANG BAO ,  HEMANTH JAGANNATHAN ,  PAUL JAMISON ,  CHOONGHYUN LEE ,  VIJAY NARAYANAN

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device is provided and has an n-channel field effect transistor (nFET) bottom junction and a p-channel field effect transistor (pFET) bottom junction. The semiconductor device includes first and second fin formations operably disposed in the nFET and pFET bottom junctions, respectively. The semiconductor device can also include an nFET metal gate layer deposited for oxygen absorption onto a high-k dielectric layer provided about the first fin formation in the nFET bottom junction and onto a pFET metal gate layer provided about the second fin formation in the pFET bottom junction. Alternatively, the semiconductor device can include an oxygen scavenging layer deposited onto the pFET metal gate layer about the second fin formation in the pFET bottom junction and, with the pFET metal gate layer deposited onto the nFET metal gate layer about the first fin formation in the nFET bottom junction, onto the pFET metal gate layer in the nFET bottom junction.

公开(公告)号：US20190189524A1

公开(公告)日：2019-06-20

申请号：US16273779

申请日：2019-02-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lisa F. Edge ,  Hemanth Jagannathan ,  Paul C. Jamison ,  Vamsi K. Paruchuri

IPC: H01L21/8238 ,  H01L29/786 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L27/12 ,  H01L27/092 ,  H01L21/84

CPC classification number: H01L21/823842 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/786

Abstract: An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.

公开(公告)号：US20190115264A1

公开(公告)日：2019-04-18

申请号：US16207274

申请日：2018-12-03

Applicant: International Business Machines Corporation

Inventor： Yogesh A. Bute ,  Hemant K. Shukla ,  Vinod K. Srivastava ,  Sandip P. Thube ,  Dharmesh V. Vadgama

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L29/517 ,  H01L29/66545 ,  H04L43/10 ,  H04L67/10 ,  H04L67/1002 ,  H04L67/1051 ,  H04L67/145 ,  H04L67/2842 ,  H04L67/42

Abstract: A method for a client-initiated leader election in a distributed system including receiving a master listener election request by at least one listener of a plurality of listeners in the distributed system, arranging a list of configured listeners in a descending priority order, the list of configured listeners comprises one or more listeners of the plurality of listeners set for connection, selecting a listener with a highest priority from the list of configured listeners, determining an availability of the selected listener, verifying a connectivity to the selected listener using a ping utility program, assigning the selected listener as a master listener based on the connectivity, and connecting to the master listener.

公开(公告)号：US20190081036A1

公开(公告)日：2019-03-14

申请号：US16179291

申请日：2018-11-02

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Yong Li

IPC: H01L27/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L27/0274 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0255 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7391 ,  H01L29/7816 ,  H01L29/785

Abstract: An ESD protection device includes a substrate structure having a substrate, first and second fins, and first and second doped regions having different conductivity types. The first doped region includes a first portion of the substrate and a first region of the first fin, the second doped region includes a second portion of the substrate, a second region of the first fin adjacent to the first region and the second fin. The ESD device also includes a first gate structure on a surface portion of the first region and on an entire surface of the second region of the first fin and including, from bottom to top, an interface layer on the surface portion of the first region and the surface portion of the second region of the first fin, a spacer, a high-k dielectric layer, a first work-function adjusting layer, a second work-function adjusting layer, and a gate.

公开(公告)号：US20180330996A1

公开(公告)日：2018-11-15

申请号：US16026209

申请日：2018-07-03

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, depositing a first nitride layer on exposed portions of the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer, the scavenging layer, and the first nitride layer to expose a portion of the first dielectric layer in an n-type field effect transistor (nFET) region of the gate stack, forming a barrier layer over the first dielectric layer and the capping layer, forming a first gate metal layer over the barrier layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：US10103065B1

公开(公告)日：2018-10-16

申请号：US15496610

申请日：2017-04-25

Applicant: International Business Machines Corporation

Inventor： Shogo Mochizuki ,  Alexander Reznicek ,  Joshua M. Rubin ,  Junli Wang

IPC: H01L29/76 ,  H01L29/423 ,  H01L21/027 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/033 ,  H01L27/12 ,  H01L29/78 ,  H01L29/165 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/78696

Abstract: Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.