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公开(公告)号：US20190189774A1
公开(公告)日：2019-06-20
申请号：US16280100
申请日：2019-02-20
IPC分类号： H01L29/66 , H01L21/8238 , H01L21/02 , H01L27/092 , H01L29/786 , H01L29/423 , H01L29/06
CPC分类号： H01L29/66553 , H01L21/0214 , H01L21/02164 , H01L21/02175 , H01L21/02255 , H01L21/02321 , H01L21/02332 , H01L21/0234 , H01L21/02532 , H01L21/823814 , H01L21/823864 , H01L21/823885 , H01L27/092 , H01L29/0653 , H01L29/42392 , H01L29/66666 , H01L29/7827 , H01L29/78618 , H01L29/78642
摘要： A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.
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2.发明申请公开(公告)号：US20200144378A1
公开(公告)日：2020-05-07
申请号：US16178725
申请日：2018-11-02
发明人： CHOONGHYUN LEE , KANGGUO CHENG , JUNTAO LI , SHOGO MOCHIZUKI
IPC分类号： H01L29/36 , H01L27/088 , H01L29/10 , H01L21/8234
摘要： A technique relates to a semiconductor device. Fins are formed of varying concentrations of germanium. Gate material is formed on the fins. Source or drain (S/D) regions are adjacent to the fins, and transistor devices include the fins.
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公开(公告)号：US20190319114A1
公开(公告)日：2019-10-17
申请号：US16454587
申请日：2019-06-27
IPC分类号： H01L29/66 , H01L21/8238 , H01L21/02 , H01L27/092 , H01L29/06 , H01L29/786 , H01L29/423 , H01L29/78
摘要： A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.
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公开(公告)号：US20190189748A1
公开(公告)日：2019-06-20
申请号：US15844923
申请日：2017-12-18
发明人： ROBIN HSIN KUO CHAO , CHOONGHYUN LEE , HENG WU , CHUN WING YEUNG , JINGYUN Zhang
IPC分类号： H01L29/10 , H01L21/8234 , H01L29/66 , H01L21/285 , H01L29/78 , H01L21/306
CPC分类号： H01L29/1037 , H01L21/28575 , H01L21/30604 , H01L21/823431 , H01L29/66446 , H01L29/66545 , H01L29/6656 , H01L29/66666 , H01L29/66795 , H01L29/7827 , H01L29/7851
摘要： A method includes forming a gate on a first fin, a second fin, and a third fin arranged on a substrate. The method includes depositing a semiconductor material on the first fin, the second fin, and the third fin. The method further includes depositing an interlayer dielectric (ILD) on the first fin, the second fin, and the third fin. The method further includes forming a first trench and a second trench through the ILD on a first side of the gate, and a third trench and a fourth trench through the ILD on a second side of the gate, the second trench coupling the second fin to the third fin, and the third trench coupling the first fin to the second fin. The method includes depositing a metal in the first trench, the second trench, the third trench, and the fourth trench.
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公开(公告)号：US20200098860A1
公开(公告)日：2020-03-26
申请号：US16680633
申请日：2019-11-12
发明人： KANGGUO CHENG , CHOONGHYUN LEE , JUNTAO LI , PENG XU
IPC分类号： H01L29/06 , H01L29/66 , H01L29/775 , H01L29/786 , B82Y10/00 , H01L29/423 , H01L29/78 , H01L21/02
摘要： A sacrificial gate stack for forming a nanosheet transistor includes a substrate. first, second and third silicon channel nanosheets formed over the substrate, and a first sandwich of germanium (Ge) containing layers disposed between the substrate and first silicon channel nanosheet. The stack also includes a second sandwich of Ge containing layers disposed between the first silicon channel nanosheet and the second silicon channel nanosheet; and a third sandwich of Ge containing layers disposed between the second silicon channel nanosheet and the third silicon channel nanosheet. Each sandwich includes first and second low Ge containing layers surrounding a silicon germanium (SiGe) sacrificial nanosheet that has a higher Ge concentration than the first and second low Ge containing layers.
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公开(公告)号：US20200058759A1
公开(公告)日：2020-02-20
申请号：US16662446
申请日：2019-10-24
发明人： Kangguo Cheng , CHOONGHYUN LEE , JUNTAO LI , HENG WU , Peng Xu
摘要： A method of fabricating air gap spacers is provided. The method includes forming gate structures to extend upwardly from a substrate with source or drain (S/D) regions disposed between the gate structures and with contact trenches defined above the S/D regions and between the gate structures. The method further includes disposing contacts in the contact trenches. The method also includes configuring the contacts to define open-ended air gap spacer trenches with the gate structures. In addition, the method includes forming a cap over the open-ended air gap spacer trenches to define the open-ended air gap spacer trenches as air gap spacers. The gate structures have an initial structure prior to and following the disposing and the configuring of the contacts and prior to and following the forming of the cap.
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公开(公告)号：US20190334011A1
公开(公告)日：2019-10-31
申请号：US15965264
申请日：2018-04-27
发明人： Kangguo Cheng , CHOONGHYUN LEE , JUNTAO LI , HENG WU , Peng Xu
摘要： A method of fabricating air gap spacers is provided. The method includes forming gate structures to extend upwardly from a substrate with source or drain (S/D) regions disposed between the gate structures and with contact trenches defined above the S/D regions and between the gate structures. The method further includes disposing contacts in the contact trenches. The method also includes configuring the contacts to define open-ended air gap spacer trenches with the gate structures. In addition, the method includes forming a cap over the open-ended air gap spacer trenches to define the open-ended air gap spacer trenches as air gap spacers. The gate structures have an initial structure prior to and following the disposing and the configuring of the contacts and prior to and following the forming of the cap.
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公开(公告)号：US20190198500A1
公开(公告)日：2019-06-27
申请号：US16293853
申请日：2019-03-06
IPC分类号： H01L27/092 , H01L29/78 , H01L29/66 , H01L21/8238 , H01L21/8234
CPC分类号： H01L27/0924 , H01L21/823431 , H01L21/823437 , H01L21/823814 , H01L21/823842 , H01L21/823885 , H01L27/092 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device is provided and has an n-channel field effect transistor (nFET) bottom junction and a p-channel field effect transistor (pFET) bottom junction. The semiconductor device includes first and second fin formations operably disposed in the nFET and pFET bottom junctions, respectively. The semiconductor device can also include an nFET metal gate layer deposited for oxygen absorption onto a high-k dielectric layer provided about the first fin formation in the nFET bottom junction and onto a pFET metal gate layer provided about the second fin formation in the pFET bottom junction. Alternatively, the semiconductor device can include an oxygen scavenging layer deposited onto the pFET metal gate layer about the second fin formation in the pFET bottom junction and, with the pFET metal gate layer deposited onto the nFET metal gate layer about the first fin formation in the nFET bottom junction, onto the pFET metal gate layer in the nFET bottom junction.
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9.发明申请公开(公告)号：US20190341314A1
公开(公告)日：2019-11-07
申请号：US15969252
申请日：2018-05-02
发明人： TAKASHI ANDO , CHOONGHYUN LEE , JINGYUN ZHANG , POUYA HASHEMI
IPC分类号： H01L21/8238 , H01L21/28 , H01L27/092 , H01L29/49 , H01L29/51 , H01L29/78
摘要： A method of fabricating a semiconductor device includes providing a high-k dielectric layer arranged on a channel region including a first transistor area and a second transistor area. The method further includes depositing a multivalent oxide layer directly on the high-k dielectric layer of the first transistor area. The method includes depositing a first work function metal on the multivalent oxide layer of the first transistor area and directly on the high-k dielectric layer of the second transistor area.
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公开(公告)号：US20190252497A1
公开(公告)日：2019-08-15
申请号：US16392018
申请日：2019-04-23
发明人： ROBIN HSIN KUO CHAO , CHOONGHYUN LEE , HENG WU , CHUN WING YEUNG , JINGYUN Zhang
IPC分类号： H01L29/10 , H01L29/66 , H01L21/306 , H01L29/78 , H01L21/8234 , H01L21/285
CPC分类号： H01L29/1037 , H01L21/28575 , H01L21/30604 , H01L21/823431 , H01L29/66446 , H01L29/66545 , H01L29/6656 , H01L29/66666 , H01L29/66795 , H01L29/7827 , H01L29/7851
摘要： A method includes forming a gate on a first fin, a second fin, and a third fin arranged on a substrate. The method includes depositing a semiconductor material on the first fin, the second fin, and the third fin. The method further includes depositing an interlayer dielectric (ILD) on the first fin, the second fin, and the third fin. The method further includes forming a first trench and a second trench through the ILD on a first side of the gate, and a third trench and a fourth trench through the ILD on a second side of the gate, the second trench coupling the second fin to the third fin, and the third trench coupling the first fin to the second fin. The method includes depositing a metal in the first trench, the second trench, the third trench, and the fourth trench.
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