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公开(公告)号：US20230284543A1
公开(公告)日：2023-09-07
申请号：US17653309
申请日：2022-03-03
发明人： KANGGUO CHENG , JUNTAO LI , ZUOGUANG LIU , ARTHUR GASASIRA
IPC分类号： H01L45/00
CPC分类号： H01L45/126 , H01L45/144 , H01L45/1641 , H01L45/06 , H01L45/1608
摘要： A semiconductor device is provided. The semiconductor device includes a heater formed on a substrate; a hardmask formed on the heater; a phase change material layer formed on a first side of the heater and the hardmask; a first electrode formed on the phase change material layer on the first side; and a second electrode formed on the substrate on a second side of the heater and the hardmask.
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2.发明申请公开(公告)号：US20200350313A1
公开(公告)日：2020-11-05
申请号：US16402471
申请日：2019-05-03
IPC分类号： H01L27/092 , H01L29/78 , H01L29/49 , H01L29/66 , H01L21/28 , H01L21/8238
摘要： A semiconductor device includes a first transistor including a first vertical fin arranged between first bottom source or drain (S/D) region and first top S/D region, and a first recessed gate stack arranged on a sidewall of the first vertical fin. A second transistor includes second vertical fin arranged between a second bottom S/D region and second top S/D region, and a second recessed gate stack arranged on a sidewall of the second vertical fin. A first spacer contacts the sidewall of the first vertical fin and on the first recessed gate stack or the second recessed gate stack. A second spacer contacts the first spacer of the first transistor or the second transistor. The second spacer is on a sidewall of the top S/D region of the first transistor or second transistor. The inner spacer and the outer spacer include different materials.
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公开(公告)号：US20200279780A1
公开(公告)日：2020-09-03
申请号：US16289903
申请日：2019-03-01
发明人： HIROKI NIIMI , PIETRO MONTANINI , KANGGUO CHENG
IPC分类号： H01L21/8234 , H01L21/768 , H01L29/66 , H01L29/78 , H01L27/088
摘要： Embodiments of the present invention are directed to techniques for forming a robust low-k bottom spacer for a vertical field effect transistor (VFET) using a spacer first, shallow trench isolation last process integration. In a non-limiting embodiment of the invention, a semiconductor fin is formed over a substrate. A first dielectric liner is formed on a sidewall of the semiconductor fin. A bottom spacer is formed over the substrate and on a sidewall of the first dielectric liner. The first dielectric liner is positioned between the semiconductor fin and the bottom spacer. Portions of the bottom spacer are removed to define a shallow trench isolation region.
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公开(公告)号：US20190107506A1
公开(公告)日：2019-04-11
申请号：US15729733
申请日：2017-10-11
发明人： KANGGUO CHENG
IPC分类号： G01N27/414 , G01N33/487 , C12Q1/68
摘要： A vertical biosensor includes a substrate and a source disposed on the substrate. A bottom spacer is disposed on the source. A chamber is disposed on the bottom spacer. A sensing gate dielectric is disposed on side and bottom surfaces of the chamber. A fin channel is disposed on opposite sides of the chamber along a direction parallel to an upper surface of the substrate facing the chamber. A back gate dielectric is disposed on the fin channel. A drain is positioned above the fin channel along a direction orthogonal to an upper surface of the substrate. A thickness of the back gate dielectric is greater than a thickness of the sensing gate dielectric.
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公开(公告)号：US20180323202A1
公开(公告)日：2018-11-08
申请号：US15585826
申请日：2017-05-03
IPC分类号： H01L27/112 , H01L23/525 , H01L23/00
CPC分类号： H01L27/11206 , H01L23/5256 , H01L23/573
摘要： A method for forming a semiconductor device includes forming a nanosheet stack comprising alternating layers of a first material and a second material on a substrate. The method further includes removing portions of the stack to form tapered stack sidewalls, which have a taper angle in relation to a horizontal surface of the substrate. The method further includes converting the second material to a resistive material. The layers that include the resistive material form one or more electrical fuses.
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公开(公告)号：US20170154961A1
公开(公告)日：2017-06-01
申请号：US15154606
申请日：2016-05-13
IPC分类号： H01L29/06 , H01L21/308 , H01L21/324 , H01L29/165 , H01L21/02
CPC分类号： H01L21/02694 , H01L21/02164 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02505 , H01L21/02532 , H01L21/02639 , H01L21/28255 , H01L21/3065 , H01L21/308 , H01L21/32055 , H01L21/324 , H01L21/7624 , H01L21/76264 , H01L21/76283 , H01L29/0649 , H01L29/0692 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/267 , H01L29/7378 , H01L29/7848 , H01L29/785 , H01L31/1816 , H01L2924/10271
摘要： A semiconductor device comprising a substrate having a region protruding from the substrate surface; a relaxed semiconductor disposed on the region; an additional semiconductor disposed on the relaxed semiconductor; and low density dielectric disposed next to and at least partially underneath the relaxed semiconductor and adjacent to the protruding region of the substrate.
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公开(公告)号：US20160315144A1
公开(公告)日：2016-10-27
申请号：US15203847
申请日：2016-07-07
IPC分类号： H01L29/06 , H01L21/8234 , H01L27/088 , H01L29/08 , H01L29/423
CPC分类号： H01L27/0886 , H01L21/28035 , H01L21/28079 , H01L21/28088 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/10826 , H01L27/10829 , H01L27/10879 , H01L27/1211 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/41791 , H01L29/42376 , H01L29/4916 , H01L29/495 , H01L29/4966 , H01L29/66545 , H01L29/66795 , H01L29/7851 , H01L29/7855
摘要： The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.
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公开(公告)号：US20150249125A1
公开(公告)日：2015-09-03
申请号：US14707775
申请日：2015-05-08
发明人： KANGGUO CHENG , ALI KHAKIFIROOZ , PRANITA KERBER , TAK H. NING
CPC分类号： H01L29/0642 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0692 , H01L29/1054 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/78 , H01L29/78687 , H01L29/78696
摘要： Methods for forming a buried-channel field-effect transistor include doping source and drain regions on a substrate with a dopant having a first type; forming a doped shielding layer on the substrate in a channel region having a second doping type opposite the first type to displace a conducting channel away from a gate-interface region; forming a gate dielectric over the doped shielding layer; and forming a gate on the gate dielectric.
摘要翻译： 用于形成掩埋沟道场效应晶体管的方法包括在具有第一类型的掺杂剂的衬底上掺杂源区和漏区; 在具有与第一类型相反的第二掺杂类型的沟道区域中的衬底上形成掺杂的屏蔽层，以使导电沟道偏离栅极 - 界面区域; 在所述掺杂屏蔽层上形成栅极电介质; 并在栅极电介质上形成栅极。
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公开(公告)号：US20230082961A1
公开(公告)日：2023-03-16
申请号：US17472145
申请日：2021-09-10
发明人： JUNTAO LI , KANGGUO CHENG , CARL RADENS , RUILONG XIE
IPC分类号： G11C13/00
摘要： A memory device is provided. The memory device includes a ReRAM memory element, and a PCM memory element that is electrically connected in parallel with the ReRAM memory element.
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10.发明申请公开(公告)号：US20200279858A1
公开(公告)日：2020-09-03
申请号：US16288906
申请日：2019-02-28
发明人： RUILONG XIE , JULIEN FROUGIER , KANGGUO CHENG
IPC分类号： H01L27/11573 , H01L27/11582
摘要： Embodiments of the present invention are directed to techniques for integrating a split gate metal-oxide-nitride-oxide-semiconductor (SG-MONOS) memory with a vertical field effect transistor (VFET). In a non-limiting embodiment of the invention, a vertical SG-MONOS memory device is formed on a first region of a substrate. The SG-MONOS memory device can include a charge storage stack, a memory gate on the charge storage stack, and a control gate vertically stacked over the charge storage stack and the memory gate. A VFET is formed on a second region of the substrate. The VFET can include a logic gate.
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