公开(公告)号：US20190019686A1

公开(公告)日：2019-01-17

申请号：US16136704

申请日：2018-09-20

申请人： International Business Machines Corporation

发明人： YANN A. MIGNOT ,  MUTHUMANICKAM SANKARAPANDIAN

IPC分类号： H01L21/308 ,  H01L21/311 ,  H01L21/027

CPC分类号： H01L21/3081 ,  H01L21/02164 ,  H01L21/0276 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/768 ,  H01L23/544 ,  H01L2223/54426

摘要： A wafer element fabrication method is provided. The wafer element fabrication method includes forming a device element on a substrate such that the device element includes an upper surface and a sidewall extending from the upper surface to the substrate. The wafer element fabrication method further includes forming an adjusted print resolution assist feature (APRAF) on the substrate such that the APRAF is smaller than the device element in at least one dimension. In addition, the wafer element fabrication method includes depositing surrounding material, which is different from materials of the APRAF, to surround the APRAF and to lie on the upper surface in abutment with the sidewall of the device element.

公开(公告)号：US20200350313A1

公开(公告)日：2020-11-05

申请号：US16402471

申请日：2019-05-03

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： RUILONG XIE ,  MUTHUMANICKAM SANKARAPANDIAN ,  CHANRO PARK ,  KANGGUO CHENG

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238

摘要： A semiconductor device includes a first transistor including a first vertical fin arranged between first bottom source or drain (S/D) region and first top S/D region, and a first recessed gate stack arranged on a sidewall of the first vertical fin. A second transistor includes second vertical fin arranged between a second bottom S/D region and second top S/D region, and a second recessed gate stack arranged on a sidewall of the second vertical fin. A first spacer contacts the sidewall of the first vertical fin and on the first recessed gate stack or the second recessed gate stack. A second spacer contacts the first spacer of the first transistor or the second transistor. The second spacer is on a sidewall of the top S/D region of the first transistor or second transistor. The inner spacer and the outer spacer include different materials.

公开(公告)号：US20180308704A1

公开(公告)日：2018-10-25

申请号：US15811111

申请日：2017-11-13

申请人： International Business Machines Corporation

发明人： YANN A. MIGNOT ,  MUTHUMANICKAM SANKARAPANDIAN

IPC分类号： H01L21/308 ,  H01L21/311 ,  H01L21/027

CPC分类号： H01L21/3081 ,  H01L21/02164 ,  H01L21/0276 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/768 ,  H01L23/544 ,  H01L2223/54426

摘要： A wafer element fabrication method is provided. The wafer element fabrication method includes forming a device element on a substrate such that the device element includes an upper surface and a sidewall extending from the upper surface to the substrate. The wafer element fabrication method further includes forming an adjusted print resolution assist feature (APRAF) on the substrate such that the APRAF is smaller than the device element in at least one dimension. In addition, the wafer element fabrication method includes depositing surrounding material, which is different from materials of the APRAF, to surround the APRAF and to lie on the upper surface in abutment with the sidewall of the device element.

公开(公告)号：US20140256145A1

公开(公告)日：2014-09-11

申请号：US13793739

申请日：2013-03-11

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： JASSEM A. ABDALLAH ,  MATTHEW E. COLBURN ,  STEVEN J. HOLMES ,  DAIJI KAWAMURA ,  CHI-CHUN LIU ,  MUTHUMANICKAM SANKARAPANDIAN ,  YUNPENG YIN

IPC分类号： H01L21/308

CPC分类号： H01L21/0337 ,  H01L21/0271

摘要： A method for defining a template for directed self-assembly (DSA) materials includes forming an etch stop layer on a neutral material, forming a mask layer on the etch stop layer and forming an anti-reflection coating (ARC) on the mask layer. A resist layer is patterned on the ARC using optical lithography to form a template pattern. The ARC and the mask layer are reactive ion etched down to the etch stop layer in accordance with the template pattern to form a template structure. The ARC is removed from the mask layer and the template structure is trimmed to reduce a width of the template structure. A wet etch is performed to remove the etch stop layer to permit the neutral material to form an undamaged DSA template for DSA materials.

摘要翻译： 用于定义用于定向自组装（DSA）材料的模板的方法包括在中性材料上形成蚀刻停止层，在蚀刻停止层上形成掩模层，并在掩模层上形成防反射涂层（ARC）。 使用光刻法在ARC上形成抗蚀剂层以形成模板图案。 ARC和掩模层根据模板图案被反应离子蚀刻到蚀刻停止层以形成模板结构。 从掩模层移除ARC，并修剪模板结构以减小模板结构的宽度。 执行湿蚀刻以去除蚀刻停止层，以允许中性材料形成用于DSA材料的未损坏的DSA模板。

公开(公告)号：US20180308703A1

公开(公告)日：2018-10-25

申请号：US15495186

申请日：2017-04-24

申请人： International Business Machines Corporation

发明人： YANN A. MIGNOT ,  MUTHUMANICKAM SANKARAPANDIAN

IPC分类号： H01L21/308 ,  H01L21/311 ,  H01L21/027

CPC分类号： H01L21/3081 ,  H01L21/02164 ,  H01L21/0276 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/768 ,  H01L23/544 ,  H01L2223/54426

摘要： A wafer element fabrication method is provided. The wafer element fabrication method includes forming a device element on a substrate such that the device element includes an upper surface and a sidewall extending from the upper surface to the substrate. The wafer element fabrication method further includes forming an adjusted print resolution assist feature (APRAF) on the substrate such that the APRAF is smaller than the device element in at least one dimension. In addition, the wafer element fabrication method includes depositing surrounding material, which is different from materials of the APRAF, to surround the APRAF and to lie on the upper surface in abutment with the sidewall of the device element.