公开(公告)号：US12132029B2

公开(公告)日：2024-10-29

申请号：US17648161

申请日：2022-01-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Chia Hu ,  Ming-Fa Chen

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/552 ,  H01L25/00 ,  H01L25/03 ,  H01L25/18

CPC分类号： H01L25/0657 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L24/94 ,  H01L25/03 ,  H01L25/50 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/08145 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/73259 ,  H01L2224/80895 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/3025 ,  H01L2224/94 ,  H01L2224/80

摘要： A method includes bonding a first device die with a second device die. The second device die is over the first device die. A passive device is formed in a combined structure including the first and the second device dies. The passive device includes a first and a second end. A gap-filling material is formed over the first device die, with the gap-filling material including portions on opposite sides of the second device die. The method further includes performing a planarization to reveal the second device die, with a remaining portion of the gap-filling material forming an isolation region, forming a first and a second through-vias penetrating through the isolation region to electrically couple to the first device die, and forming a first and a second electrical connectors electrically coupling to the first end and the second end of the passive device.

公开(公告)号：US12132021B2

公开(公告)日：2024-10-29

申请号：US18354668

申请日：2023-07-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Hao Tsai ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L24/09 ,  H01L21/56 ,  H01L21/76816 ,  H01L23/3107 ,  H01L24/17 ,  H01L24/33 ,  H01L2224/02379 ,  H01L2924/35121

摘要： A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.

公开(公告)号：US12131974B2

公开(公告)日：2024-10-29

申请号：US17353798

申请日：2021-06-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chin-Fu Kao ,  Chen-Shien Chen

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L21/54 ,  H01L23/00 ,  H01L23/18 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/3675 ,  H01L21/4882 ,  H01L21/54 ,  H01L23/18 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/182

摘要： A semiconductor package includes a substrate, a package structure, a lid structure, and a thermal spreader layer. The package structure is disposed on the substrate, wherein the package structure includes a plurality of device dies and a filling material filling a gap between adjacent two of the plurality of device dies. The lid structure is disposed over substrate and covering the package structure. The thermal spreader layer is disposed between the lid structure and the package structure, wherein the thermal spreader layer has a profile that is discontinuous in thickness at a gap region corresponding to the gap.

公开(公告)号：US12131896B2

公开(公告)日：2024-10-29

申请号：US17461040

申请日：2021-08-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Kei-Wei Chen ,  Chih Hung Chen

IPC分类号： H01L21/02 ,  A46B13/00 ,  B08B1/12 ,  B08B1/32 ,  B24B7/22

CPC分类号： H01L21/02016 ,  A46B13/001 ,  B08B1/12 ,  B08B1/32 ,  B24B7/228 ,  H01L21/02024 ,  H01L21/02054 ,  A46B2200/3073 ,  A46B2200/3093

摘要： A method of cleaning and polishing a backside surface of a semiconductor wafer is provided. The method includes placing an abrasive brush, comprising an abrasive tape wound around an outer surface of a brush member of the abrasive brush, on the backside surface of the semiconductor wafer. The method also includes rotating the brush member to polish the backside surface of the semiconductor wafer by abrasive grains formed on the abrasive tape and to clean the backside surface of the semiconductor wafer by the brush member which is not covered by the abrasive tape.

公开(公告)号：US12131770B1

公开(公告)日：2024-10-29

申请号：US18354399

申请日：2023-07-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Atul Katoch

IPC分类号： G11C11/408 ,  G11C11/4076 ,  G11C11/4096

CPC分类号： G11C11/4085 ,  G11C11/4076 ,  G11C11/4096

摘要： A memory circuit includes a plurality of word lines, a word line driver coupled to a first end of the plurality of word lines and configured to activate each word line of the plurality of word lines, a local I/O circuit configured to generate a pulse signal corresponding to the word line driver activating any word line of the plurality of word lines, a first node configured to carry a first power supply voltage, and a booster circuit coupled to a second end of the plurality of word lines, the local I/O circuit, and the first node. The booster circuit is configured to couple each word line of the plurality of word lines to the first node responsive to the pulse signal and to the corresponding word line being activated by the word line driver.

公开(公告)号：US20240357789A1

公开(公告)日：2024-10-24

申请号：US18362212

申请日：2023-07-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Oreste Madia ,  Gerben Doornbos

IPC分类号： H10B10/00 ,  H01L23/528 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H10B10/125 ,  H01L23/5283 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/78696

摘要： A memory device includes a first n-type transistor and a second n-type transistor formed of a first channel extending along a vertical direction and wrapped by first, second, third, fourth, and fifth metal tracks; a third n-type transistor and a fourth n-type transistor formed of a second channel extending along the vertical direction and is wrapped by fourth, sixth, seventh, eighth, and ninth metal tracks; a first p-type transistor formed of a third channel extending along the vertical direction and is wrapped by second, third, and tenth metal tracks; and a second p-type transistor formed of a fourth channel extending along the vertical direction and is wrapped by sixth, seventh, and tenth metal tracks.

公开(公告)号：US20240357788A1

公开(公告)日：2024-10-24

申请号：US18756363

申请日：2024-06-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hidehiro FUJIWARA ,  Chih-Yu LIN ,  Hsien-Yu PAN ,  Yasutoshi OKUNO ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC分类号： H10B10/00 ,  G06F30/392 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC分类号： H10B10/12 ,  G06F30/392 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207

摘要： A memory circuit includes a first pull down transistor, a first pass gate transistor coupled to the first pull down transistor, a second pull down transistor, a second pass gate transistor and a first metal contact. The second pull down transistor has a first active region located on a first level. The second pass gate transistor has a second active region located on the first level, and being coupled to the second pull down transistor. The first metal contact extends from the first active region to the second active region, being located on a second level, and electrically coupling a drain of the second pull down transistor to a drain of the second pass gate transistor. The first pass gate transistor, the second pass gate transistor, the first pull down transistor and the second pull down transistor are part of a four transistor (4T) memory cell.

公开(公告)号：US20240355927A1

公开(公告)日：2024-10-24

申请号：US18305514

申请日：2023-04-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Szu-Ying CHEN ,  Sen-Hong SYUE ,  Chi On CHUI

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L2029/7858

摘要： A method for forming a semiconductor device structure is provided. The method includes forming an expansion film over a substrate. The substrate has a base portion, a first fin, and a second fin over the base portion. The method includes forming an isolation layer over the expansion film. The method includes annealing the expansion film, the substrate, and the isolation layer. The method includes partially removing the isolation layer and the expansion film to expose the first upper portion of the first fin and the second upper portion of the second fin. The method includes forming a gate stack wrapping around the first upper portion of the first fin and the second upper portion of the second fin.

公开(公告)号：US20240355901A1

公开(公告)日：2024-10-24

申请号：US18302177

申请日：2023-04-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jung-Hung CHANG ,  Shih-Cheng CHEN ,  Chih-Hao WANG ,  Chia-Cheng TSAI ,  Kuo-Cheng CHIANG ,  Zhi-Chang LIN ,  Chien-Ning YAO ,  Tsung-Han CHUANG

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC分类号： H01L29/66439 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/775

摘要： A method for forming a semiconductor device structure includes forming a fin structure, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack wrapped around the fin structure and forming a spacer layer extending along sidewalls of the fin structure and the gate stack. The method further includes partially removing the fin structure and the spacer layer to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers. A remaining portion of the spacer layer forms a gate spacer. In addition, the method includes forming an inner spacer layer along a sidewall and a bottom of the recess and partially removing the inner spacer layer using an isotropic etching process. Remaining portions of the inner spacer layers form multiple inner spacers. The method includes forming an epitaxial structure in the recess.

公开(公告)号：US20240355877A1

公开(公告)日：2024-10-24

申请号：US18303698

申请日：2023-04-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Lung TUNG ,  Xiaodong WANG ,  Jhon-Jhy LIAW

IPC分类号： H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/0673 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

摘要： Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first well region and longitudinally oriented along a first direction and a second well region adjoining the first well region in a second direction. The semiconductor structure also includes a dielectric wall structure formed over a boundary between the first well region and the second well region and first channel structures vertically suspended over a first region of the first well region and laterally attached to a first sidewall surface of the dielectric wall structure. The semiconductor structure includes a first gate structure wrapping around the first channel structures and second channel structures vertically suspended over a second region of the first well region and a second gate structure wrapping around the second channel structures. In addition, the first channel structures is smaller than the second channel structures.