公开(公告)号：US20230143543A1

公开(公告)日：2023-05-11

申请号：US17819936

申请日：2022-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongsun Kim ,  Shigenobu Maeda ,  Myoungkyu Park

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/6656 ,  H01L29/66545

Abstract: A semiconductor device includes an active fin protruding from a substrate, extending in a first direction, and defined by a device isolation layer. Gate structures intersect the active fin and extend in a second direction. Each of the gate structures includes a gate and gate spacers on side surfaces of the gate. Epitaxial layers are disposed on the active fin, on opposite sides of the gate structure, and include a first epitaxial layer providing a drain region and a second epitaxial layer providing a source region. The gate spacers include a first spacer disposed between the first epitaxial layer and the gate. The first spacer includes a first region extending in a third direction, along a side surface of the gate, and a second region extending from a lower portion of the first region in a direction away from the gate.

公开(公告)号：US09941360B2

公开(公告)日：2018-04-10

申请号：US15340199

申请日：2016-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shigenobu Maeda ,  Seunghan Seo ,  Yeohyun Sung

IPC: H01L29/165 ,  H01L29/16 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/20 ,  H01L29/22 ,  H01L29/78 ,  H01L29/267 ,  H01L29/778 ,  H01L29/786 ,  H01L29/24 ,  H01L29/51

CPC classification number: H01L29/1606 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/24 ,  H01L29/267 ,  H01L29/517 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786

Abstract: A field effect transistor and a semiconductor device including the same are provided. The semiconductor device may include a channel layer, which is provided on a substrate and includes a two-dimensional atomic layer made of a first material, and a source/drain layer, which is provided on the substrate and includes a second material. The first material may be one of phosphorus allotropes, the second material may be one of carbon allotropes, and the channel layer and the source/drain layer may be connected to each other by covalent bonds between the first and second materials.

公开(公告)号：US09831240B2

公开(公告)日：2017-11-28

申请号：US14167236

申请日：2014-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Yeop Park ,  Leonelli Daniele ,  Shigenobu Maeda ,  Han-Su Oh ,  Woong-Gi Kim ,  Jong-Hyuk Lee ,  Ju-Seob Jeong

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a gate on a substrate, a gate insulating layer along a sidewall and a bottom surface of the gate, and an L-shaped spacer structure on both sidewalls of the gate. A structure extends the distance between the gate and source/drain regions to either side of the gate.

公开(公告)号：US09728601B2

公开(公告)日：2017-08-08

申请号：US15058466

申请日：2016-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Woo Kim ,  Shigenobu Maeda ,  Young-Moon Choi ,  Yong-Bum Kwon ,  Chang-Woo Sohn ,  Do-Sun Lee

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8238

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.

公开(公告)号：US09698268B2

公开(公告)日：2017-07-04

申请号：US15158859

申请日：2016-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Bo-Ram Kim

IPC: H01L21/70 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L27/092 ,  H01L27/108 ,  H01L27/11 ,  H01L29/06 ,  H01L29/267

CPC classification number: H01L29/785 ,  H01L27/0924 ,  H01L27/108 ,  H01L27/11 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/66818

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device includes forming a semiconductor layer on a fin, where the fin and the semiconductor layer include first and second semiconductor materials, respectively. Moreover, the method includes defining first and second active fins that include the second semiconductor material, by removing at least a portion of the fin. Related semiconductor devices are also provided.

公开(公告)号：US09679975B2

公开(公告)日：2017-06-13

申请号：US14823229

申请日：2015-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Zhenhua Wu ,  Krishna Bhuwalka ,  Sangsu Kim ,  Shigenobu Maeda

IPC: H01L31/00 ,  H01L29/74 ,  H01L23/52 ,  H01L29/66 ,  H01L29/267 ,  H01L27/092 ,  H01L27/088 ,  H01L29/10 ,  H01L29/16 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/267 ,  H01L21/02524 ,  H01L21/02538 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1606 ,  H01L29/165

Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.

公开(公告)号：US20170033107A1

公开(公告)日：2017-02-02

申请号：US15159978

申请日：2016-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Hak HONG ,  Sungil Park ,  Toshinori Fukai ,  Shigenobu Maeda ,  Sada-aki Masuoka ,  Sanghyun Lee ,  Keon Yong Cheon ,  Hock-Chun Chin

IPC: H01L27/092 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/78 ,  H01L29/7846 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including at least one metal-oxide-semiconductor field-effect transistor (MOSFET) region defined by a device isolation layer and having an active pattern extending in a first direction on the MOSFET region, a gate electrode intersecting the active pattern on the substrate and extending in a second direction intersecting the first direction, and a first gate separation pattern adjacent to the MOSFET region when viewed from a plan view and dividing the gate electrode into segments spaced apart from each other in the second direction. The first gate separation pattern has a tensile strain when the MOSFET region is a P-channel. MOSFET (PMOSFET) region. The first gate separation pattern has a compressive strain when the MOSFET region is an N-channel MOSFET (NMOSFET) region.

Abstract translation: 半导体器件包括：衬底，其包括由器件隔离层限定的至少一个金属氧化物半导体场效应晶体管（MOSFET）区域，并且具有在MOSFET区域上沿第一方向延伸的有源图案;栅极电极与有源 并且沿与第一方向相交的第二方向延伸，以及从平面图观察与MOSFET区域相邻的第一栅极分离图案，并且将栅电极在第二方向上彼此间隔开。 当MOSFET区域为P沟道时，第一栅极分离图案具有拉伸应变。 MOSFET（PMOSFET）区域。 当MOSFET区域是N沟道MOSFET（NMOSFET）区域时，第一栅极分离图案具有压缩应变。

公开(公告)号：US20160379980A1

公开(公告)日：2016-12-29

申请号：US15211012

申请日：2016-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Jeong Hwan Yang

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1052 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848

Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

公开(公告)号：US09293701B2

公开(公告)日：2016-03-22

申请号：US14527176

申请日：2014-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Juyoun Kim ,  Shigenobu Maeda ,  Jihoon Yoon ,  Sungman Lim

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

Abstract: A variable resistance memory device includes a gate pattern and a dummy gate pattern provided at the same level on a substrate, a first contact pattern provided on the dummy gate pattern, and a variable resistance pattern provided between the dummy gate pattern and the first contact pattern. The gate pattern and the dummy gate pattern define conductive electrodes of functional and non-functional transistors, respectively. The first contact pattern and the dummy gate pattern define upper and lower electrodes on the variable resistance pattern, respectively. Related fabrication methods are also discussed.

Abstract translation: 可变电阻存储器件包括栅极图案和设置在基板上相同电平上的虚拟栅极图案，设置在伪栅极图案上的第一接触图案和设置在伪栅极图案和第一接触图案之间的可变电阻图案 。 栅极图案和虚拟栅极图案分别限定功能和非功能晶体管的导电电极。 第一接触图案和伪栅极图案分别限定可变电阻图案上的上电极和下电极。 还讨论了相关的制造方法。

公开(公告)号：US20160005864A1

公开(公告)日：2016-01-07

申请号：US14723673

申请日：2015-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： TaeYong Kwon ,  Shigenobu Maeda ,  David Seo ,  Jae-Hwan Lee

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/7849 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785

Abstract: A MOSFET may be formed with a strain-inducing mismatch of lattice constants that improves carrier mobility. In exemplary embodiments a MOSFET includes a strain-inducing lattice constant mismatch that is not undermined by a recessing step. In some embodiments a source/drain pattern is grown without a recessing step, thereby avoiding problems associated with a recessing step. Alternatively, a recessing process may be performed in a way that does not expose top surfaces of a strain-relaxed buffer layer. A MOSFET device layer, such as a strain-relaxed buffer layer or a device isolation layer, is unaffected by a recessing step and, as a result, strain may be applied to a channel region without jeopardizing subsequent formation steps.

Abstract translation: 可以形成MOSFET，其具有改善载流子迁移率的晶格常数的应变诱导失配。 在示例性实施例中，MOSFET包括不会被凹陷步骤破坏的应变诱导晶格常数失配。 在一些实施例中，源/漏图案在没有凹陷步骤的情况下生长，从而避免与凹陷步骤相关的问题。 或者，可以以不暴露应变松弛缓冲层的顶表面的方式执行凹陷处理。 诸如应变松弛缓冲层或器件隔离层的MOSFET器件层不受凹陷步骤的影响，结果可能将应变施加到沟道区而不会影响随后的形成步骤。