公开(公告)号：US20170069570A1

公开(公告)日：2017-03-09

申请号：US15229518

申请日：2016-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon Yoon ,  Shincheol Min ,  Hyun-Min Choi

IPC: H01L23/525 ,  H01L21/66 ,  H01L27/112

CPC classification number: H01L23/5256 ,  H01L22/14 ,  H01L27/11206 ,  H01L27/11582 ,  H01L28/00

Abstract: In a semiconductor device and a method of manufacturing the same a fuse structure may be formed during formation of first to third contact plugs connected to a transistor. The fuse structure may include first and second fuse contact plugs having the same height as the first and second contact plugs, and a connection pattern having the same height as the third contact plug. The connection pattern may be connected between the first and second fuse contact plugs.

Abstract translation: 在半导体器件及其制造方法中，可在形成连接到晶体管的第一至第三接触插塞的形成期间形成熔丝结构。 熔丝结构可以包括具有与第一和第二接触插塞相同的高度的第一和第二熔丝接触插塞，以及具有与第三接触插塞相同高度的连接图案。 连接图案可以连接在第一和第二熔丝接触插头之间。

公开(公告)号：US09887202B2

公开(公告)日：2018-02-06

申请号：US15334411

申请日：2016-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda ,  Jihoon Yoon ,  Sungman Lim

IPC: H01L29/78 ,  H01L27/112 ,  H01L29/06 ,  H01L29/423 ,  H01L23/522 ,  H01L23/525 ,  H01L27/02

CPC classification number: H01L27/11206 ,  H01L23/5226 ,  H01L23/5252 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/42372 ,  H01L29/785 ,  H01L29/7851

Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.

公开(公告)号：US09293701B2

公开(公告)日：2016-03-22

申请号：US14527176

申请日：2014-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Juyoun Kim ,  Shigenobu Maeda ,  Jihoon Yoon ,  Sungman Lim

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

Abstract: A variable resistance memory device includes a gate pattern and a dummy gate pattern provided at the same level on a substrate, a first contact pattern provided on the dummy gate pattern, and a variable resistance pattern provided between the dummy gate pattern and the first contact pattern. The gate pattern and the dummy gate pattern define conductive electrodes of functional and non-functional transistors, respectively. The first contact pattern and the dummy gate pattern define upper and lower electrodes on the variable resistance pattern, respectively. Related fabrication methods are also discussed.

Abstract translation: 可变电阻存储器件包括栅极图案和设置在基板上相同电平上的虚拟栅极图案，设置在伪栅极图案上的第一接触图案和设置在伪栅极图案和第一接触图案之间的可变电阻图案 。 栅极图案和虚拟栅极图案分别限定功能和非功能晶体管的导电电极。 第一接触图案和伪栅极图案分别限定可变电阻图案上的上电极和下电极。 还讨论了相关的制造方法。

公开(公告)号：US20150144862A1

公开(公告)日：2015-05-28

申请号：US14527176

申请日：2014-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Juyoun Kim ,  Shigenobu Maeda ,  Jihoon Yoon ,  Sungman Lim

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

Abstract: A variable resistance memory device includes a gate pattern and a dummy gate pattern provided at the same level on a substrate, a first contact pattern provided on the dummy gate pattern, and a variable resistance pattern provided between the dummy gate pattern and the first contact pattern. The gate pattern and the dummy gate pattern define conductive electrodes of functional and non-functional transistors, respectively. The first contact pattern and the dummy gate pattern define upper and lower electrodes on the variable resistance pattern, respectively. Related fabrication methods are also discussed.

Abstract translation: 可变电阻存储器件包括栅极图案和设置在基板上相同电平上的虚拟栅极图案，设置在伪栅极图案上的第一接触图案和设置在伪栅极图案和第一接触图案之间的可变电阻图案 。 栅极图案和虚拟栅极图案分别限定功能和非功能晶体管的导电电极。 第一接触图案和伪栅极图案分别限定可变电阻图案上的上电极和下电极。 还讨论了相关的制造方法。

公开(公告)号：US10685968B2

公开(公告)日：2020-06-16

申请号：US15399243

申请日：2017-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon Yoon ,  Hyun-Min Choi

IPC: H01L27/112 ,  H01L23/525 ,  H01L23/522

Abstract: A semiconductor device is disclosed. The semiconductor device including writing and reading gate electrodes respectively on first and second active regions on a substrate, a first gate insulation pattern between the first active region and the writing gate electrode, a second gate insulation pattern between the second active region and the reading gate electrode, first and second source/drain junction regions in the first and second active regions at sides of the writing and reading gate electrodes, and a connection structure that connects the first and second source/drain junction regions. The first active region has the same conductivity type as the source/drain junction regions. The second active region has a different conductivity type from the source/drain junction regions.

公开(公告)号：US10192823B2

公开(公告)日：2019-01-29

申请号：US15229518

申请日：2016-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon Yoon ,  Shincheol Min ,  Hyun-Min Choi

IPC: H01L23/62 ,  H01L23/525 ,  H01L27/112 ,  H01L21/66 ,  H01L27/11582

Abstract: In a semiconductor device and a method of manufacturing the same a fuse structure may be formed during formation of first to third contact plugs connected to a transistor. The fuse structure may include first and second fuse contact plugs having the same height as the first and second contact plugs, and a connection pattern having the same height as the third contact plug. The connection pattern may be connected between the first and second fuse contact plugs.

公开(公告)号：US09502425B2

公开(公告)日：2016-11-22

申请号：US14532152

申请日：2014-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda ,  Jihoon Yoon ,  Sungman Lim

IPC: H01L27/112 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L27/02

CPC classification number: H01L27/11206 ,  H01L23/5226 ,  H01L23/5252 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/42372 ,  H01L29/785 ,  H01L29/7851

Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.

Abstract translation: 本发明构思提供半导体器件及其制造方法。 一个半导体器件包括衬底，设置在衬底上的器件隔离层，由器件隔离层限定并且具有高于器件隔离层的顶表面的顶表面的翅片型有源图案，设置在器件隔离层上的第一导电线 翅片型有源图案的边缘部分和与鳍式有源图案的边缘部分相邻的器件隔离层，以及设置在鳍式有源图案和第一导电线之间的绝缘薄层。 第一导线形成可以施加写入电压的反熔丝的栅电极。