公开(公告)号：US09679975B2

公开(公告)日：2017-06-13

申请号：US14823229

申请日：2015-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Zhenhua Wu ,  Krishna Bhuwalka ,  Sangsu Kim ,  Shigenobu Maeda

IPC: H01L31/00 ,  H01L29/74 ,  H01L23/52 ,  H01L29/66 ,  H01L29/267 ,  H01L27/092 ,  H01L27/088 ,  H01L29/10 ,  H01L29/16 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/267 ,  H01L21/02524 ,  H01L21/02538 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1606 ,  H01L29/165

Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.

公开(公告)号：US09634092B2

公开(公告)日：2017-04-25

申请号：US15046455

申请日：2016-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna Kumar Bhuwalka ,  Zhenhua Wu ,  Uihui Kwon ,  Keunho Lee

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/0673 ,  H01L29/0676 ,  H01L29/1037 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7782 ,  H01L29/785 ,  H01L29/78696

Abstract: Provided is a finFET device. The finFET device may include an active region which protrudes vertically from a substrate, a channel region disposed on a center of the active region, a drain region disposed on one side surface of the channel region, and a source region disposed on the other side surface of the channel region, a gate insulating layer formed on two opposing side surfaces of the channel region and having a U-shaped cross-section, gate spacers formed on outer surfaces of the gate insulating layer, drain spacers formed on two opposing side surfaces of the drain region, and source spacers formed on two opposing side surfaces of the source region, and at least one of the two side surfaces of the drain region has a tapered part.

公开(公告)号：US10418448B2

公开(公告)日：2019-09-17

申请号：US15591405

申请日：2017-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Zhenhua Wu ,  Krishna Bhuwalka ,  Sangsu Kim ,  Shigenobu Maeda

IPC: H01L29/267 ,  H01L27/092 ,  H01L27/088 ,  H01L29/10 ,  H01L29/16 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/06

Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.

公开(公告)号：US20170243942A1

公开(公告)日：2017-08-24

申请号：US15591405

申请日：2017-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Zhenhua Wu ,  Krishna Bhuwalka ,  Sangsu Kim ,  Shigenobu Maeda

IPC: H01L29/267 ,  H01L21/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/267 ,  H01L21/02524 ,  H01L21/02538 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1606 ,  H01L29/165

Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.