公开(公告)号：US08993380B2

公开(公告)日：2015-03-31

申请号：US13791305

申请日：2013-03-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shang-Yun Hou ,  Der-Chyang Yeh ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/3157 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Provided is a chip package structure and a method for forming the chip package. The method includes bonding a plurality of first dies on a carrier, encapsulating in a first molding compound the first dies on the carrier, coupling a plurality of second dies on the first dies using conductive elements, adding an underfill between the second dies and the first dies surrounding the conductive elements, and encapsulating in a second molding compound the second dies and the underfill. The chip package comprises a chip encapsulated in a molding compound, and a larger chip coupled to the first chip via conductive elements, wherein the conductive elements are encapsulated in an underfill between the chip and the larger chip without an interposer, and wherein the larger chip and the underfill are encapsulated in a second molding compound in contact with the molding compound.

Abstract translation: 提供了一种芯片封装结构和用于形成芯片封装的方法。 该方法包括：将多个第一模具结合在载体上，将第一模具封装在载体上的第一模具中，使用导电元件将第一模具上的多个第二模具连接起来，在第二模具与第一模具之间加入底部填充物 围绕导电元件的模具，并且将第二模具和底部填充物封装在第二模塑复合物中。 芯片封装包括封装在模制化合物中的芯片，以及通过导电元件耦合到第一芯片的较大芯片，其中导电元件封装在芯片和较大芯片之间的底部填充物，而没有插入器，并且其中较大芯片 并将底部填充物封装在与模塑料接触的第二模塑料中。

公开(公告)号：US20150069580A1

公开(公告)日：2015-03-12

申请号：US14542317

申请日：2014-11-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Yu Tsai ,  Shih-Hui Wang ,  Chien-Ming Chiu ,  Chia-Ho Chen ,  Fang Wen Tsai ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/30604 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/13

Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

Abstract translation: 根据实施例，结构包括具有第一区域和第二区域的基板; 穿过基板的第一区域的贯穿基板通孔（TSV）; 在所述衬底的所述第二区域上方的隔离层，所述隔离层具有凹部; 以及在所述隔离层的所述凹部中的导电材料，所述隔离层设置在所述凹部中的所述导电材料和所述基板之间。

公开(公告)号：US20150048503A1

公开(公告)日：2015-02-19

申请号：US13968730

申请日：2013-08-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sao-Ling Chiu ,  Kuo-Ching Hsu ,  Wei-Cheng Wu ,  Ping-Kang Huang ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias.

Abstract translation: 封装结构包括插入件，模具并结合到插入件，以及底层并结合到插入件的印刷电路板（PCB）。 内插器不含晶体管（添加晶体管），并且包括半导体衬底，半导体衬底上的互连结构，硅衬底中的通孔以及硅衬底的背侧上的再分配线。 互连结构和再分配线通过通孔电耦合。

公开(公告)号：US08952506B2

公开(公告)日：2015-02-10

申请号：US14221001

申请日：2014-03-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Wen-Chih Chiou ,  Fang Wen Tsai ,  Chen-Yu Tsai

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/00 ,  H01L21/683 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/0217 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76871 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05018 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05559 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2224/05552

Abstract: A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.

Abstract translation: 公开了一种制造硅通孔的系统和方法。 一个实施例包括用从衬底突出的衬垫形成通孔硅通孔。 钝化层形成在衬底和穿通硅通孔之上，钝化层和衬垫从通硅通孔的侧壁凹陷。 然后可以将导电材料形成为与通孔硅通孔的两个侧壁和顶表面接触。

公开(公告)号：US20150035134A1

公开(公告)日：2015-02-05

申请号：US13957727

申请日：2013-08-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wensen Hung ,  Szu-Po Huang ,  Kim Hong Chen ,  Shin-Puu Jeng

IPC: H01L23/34

CPC classification number: H01L25/0657 ,  H01L23/34 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/42 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion not overlapped by the first die. A first Thermal Interface Material (TIM) is over and contacting a top surface of the first die. A heat dissipating lid has a first bottom surface contacting the first TIM. A second TIM is over and contacting the second portion of the second die. A heat dissipating ring is over and contacting the second TIM.

Abstract translation: 包装包括第一管芯和第一管芯下​​面的第一管芯和与第一管芯相同的第一管芯堆叠。 第二模具包括与第一模具重叠的第一部分和不与第一模具重叠的第二部分。 第一个热界面材料（TIM）结束并接触第一个模具的顶面。 散热盖具有接触第一TIM的第一底面。 第二TIM结束并接触第二模具的第二部分。 散热环结束并与第二个TIM接触。

公开(公告)号：US20140361432A1

公开(公告)日：2014-12-11

申请号：US14466877

申请日：2014-08-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Chieh Hsieh ,  Cheng-Lin Huang ,  Po-Hao Tsai ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Shin-Puu Jeng

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11616 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13013 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1362 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/16056 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81121 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/384 ,  H01L2924/3841 ,  H01L2924/00014

Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

Abstract translation: 提供了一种用于导电柱的系统和方法。 一个实施例包括具有位于其外边缘周围的沟槽的导电柱。 当在导电柱上形成导电凸块时，沟槽用于引导诸如焊料的导电材料。 导电柱然后可以通过导电材料电连接到另一接触件。

公开(公告)号：US08906798B2

公开(公告)日：2014-12-09

申请号：US13714828

申请日：2012-12-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Yu Wang ,  Tzu-Wei Chiu ,  Shin-Puu Jeng

IPC: H01L21/60

CPC classification number: H01L23/3192 ,  H01L21/76804 ,  H01L21/76885 ,  H01L23/293 ,  H01L23/31 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0215 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/10156 ,  H01L2224/131 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/06 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A mounting structure for a semiconductor device is formed to include a stepwise stress buffer layer under a stepwise UBM structure.

Abstract translation: 半导体器件的安装结构形成为包括阶梯式UBM结构下的阶梯应力缓冲层。

公开(公告)号：US20140339696A1

公开(公告)日：2014-11-20

申请号：US14448356

申请日：2014-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Jui-Pin Hung ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L23/48 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/214

Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.

Abstract translation: 封装包括具有基板的器件裸片。 模塑料与基材的侧壁接触。 金属焊盘在基板上。 钝化层具有覆盖金属焊盘的边缘部分的部分。 金属支柱已经过去并与金属垫接触。 介电层位于钝化层的上方。 由模塑料或聚合物形成的包装材料在电介质层的上面。 电介质层包括位于钝化层和封装材料之间的底部，以及在金属柱的侧壁和封装材料的侧壁之间的侧壁部分。 聚合物层在包装材料，模塑料和金属支柱之上。 后钝化互连（PPI）延伸到聚合物层中。 焊球在PPI上方，并通过PPI电耦合到金属焊盘。

公开(公告)号：US20140248745A1

公开(公告)日：2014-09-04

申请号：US14275488

申请日：2014-05-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/85 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An embodiment 3DIC device includes a semiconductor chip, a die, and a polymer. The semiconductor chip includes a semiconductor substrate, wherein the semiconductor substrate comprises a first edge, and a dielectric layer over the semiconductor substrate. The die is disposed over and bonded to the semiconductor chip. The polymer is molded onto the semiconductor chip and the die. The polymer includes a portion level with the dielectric layer, wherein the portion of the polymer comprises a second edge vertically aligned to the first edge of the semiconductor substrate and a third edge contacting the dielectric layer, wherein the second and the third edges are opposite edges of the portion of the polymer.

Abstract translation: 实施例3DIC装置包括半导体芯片，模具和聚合物。 半导体芯片包括半导体衬底，其中半导体衬底包括第一边缘和半导体衬底上的电介质层。 芯片设置在半导体芯片上并结合到半导体芯片上。 聚合物模制在半导体芯片和模具上。 聚合物包括具有电介质层的部分水平，其中聚合物的该部分包括垂直对准半导体衬底的第一边缘的第二边缘和与电介质层接触的第三边缘，其中第二和第三边缘是相对的边缘 的聚合物部分。

公开(公告)号：US20140217610A1

公开(公告)日：2014-08-07

申请号：US14249637

申请日：2014-04-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Shang-Yun Hou ,  Kim Hong Chen ,  Wensen Hung ,  Szu-Po Huang

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/11 ,  H01L2224/11002 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/1183 ,  H01L2224/11848 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81805 ,  H01L2224/83 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014

Abstract: Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted to at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects.

Abstract translation: 本文公开了一种形成装置的方法，包括将多个第一互连件安装在一个或多个第一集成电路管芯上。 一个或多个第二集成电路管芯安装在插入件的第一侧上。 该插入件安装在第二侧，并与第一集成电路管芯相连，多个第一互连件设置在插入件外部。 通过将第一互连件附接到衬底，将衬底安装到衬底的第一侧，衬底通过第一互连与一个或多个第一集成电路管芯信号通信。