公开(公告)号：US09620471B2

公开(公告)日：2017-04-11

申请号：US14723378

申请日：2015-05-27

Applicant: Infineon Technologies Americas Corp.

Inventor： Martin Standing ,  Robert J. Clarke

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/482 ,  H01L23/29 ,  H01L29/20 ,  H01L29/201 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L24/33 ,  H01L23/296 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/4951 ,  H01L23/49562 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/41725 ,  H01L29/4232 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29611 ,  H01L2224/29644 ,  H01L2224/2969 ,  H01L2224/81054 ,  H01L2224/8121 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0715 ,  H01L2924/1032 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/29075 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A power semiconductor package that includes a semiconductor die having at least two power electrodes and a conductive clip electrically and mechanically coupled to each power electrode.

公开(公告)号：US20150262967A1

公开(公告)日：2015-09-17

申请号：US14640219

申请日：2015-03-06

Applicant: RAYTHEON COMPANY

Inventor： Cody B. Moody

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/83 ,  H01L21/563 ,  H01L23/10 ,  H01L24/03 ,  H01L24/09 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/26135 ,  H01L2224/29023 ,  H01L2224/29035 ,  H01L2224/29562 ,  H01L2224/2957 ,  H01L2224/29609 ,  H01L2224/29611 ,  H01L2224/29624 ,  H01L2224/29644 ,  H01L2224/29686 ,  H01L2224/32055 ,  H01L2224/32148 ,  H01L2224/32502 ,  H01L2224/32506 ,  H01L2224/83054 ,  H01L2224/8309 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2224/83825 ,  H01L2224/83948 ,  H01L2224/94 ,  H01L2924/01032 ,  H01L2924/01322 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring.

Abstract translation: 密封的半导体晶片封装，其包括在第一晶片上的第一结合环，其面向第二晶片上的第二结合环的互补表面。 该封装包括形成在第一结合环的表面上的第一材料的第一和第二间隔，第一和第二间隔具有第一厚度。 该封装还包括共晶合金（不一定是共晶的，通常它是一种不是特定于元素的共晶比的合金），由第二种材料形成，并且第一种材料在第一和第二种之间形成气密封 晶片，通过将第一和第二晶片加热到高于第二材料的回流温度并低于第一材料的回流温度的温度而形成的共晶合金，其中共晶合金填充第一和第二间隙之间的体积， 和第二结合环，并且其中所述支架在所述第一结合环和所述第二结合环之间保持预定的距离。

公开(公告)号：US08377798B2

公开(公告)日：2013-02-19

申请号：US12943281

申请日：2010-11-10

Applicant: Jung-Huei Peng ,  Hsin-Ting Huang ,  Yao-Te Huang ,  Shang-Ying Tsai ,  Ping-Yin Liu

Inventor： Jung-Huei Peng ,  Hsin-Ting Huang ,  Yao-Te Huang ,  Shang-Ying Tsai ,  Ping-Yin Liu

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/311

CPC classification number: H01L25/0657 ,  B81C1/00269 ,  B81C2203/019 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/2746 ,  H01L2224/2782 ,  H01L2224/2783 ,  H01L2224/27831 ,  H01L2224/2784 ,  H01L2224/27848 ,  H01L2224/29082 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29117 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29611 ,  H01L2224/29617 ,  H01L2224/29644 ,  H01L2224/29647 ,  H01L2224/29655 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/3207 ,  H01L2224/32148 ,  H01L2224/32505 ,  H01L2224/83011 ,  H01L2224/83012 ,  H01L2224/83014 ,  H01L2224/83121 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/10157 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/01014 ,  H01L2924/01013 ,  H01L2224/83

Abstract: A method for wafer to wafer bonding in semiconductor packaging provides for roughening the bonding surfaces in one embodiment. Also provided is a method for passivating the bonding surfaces with a lower melting point material that becomes forced away from the bonding interface during bonding. Also provided is a method for forming an eutectic at the bonding interface to reduce the impact of any native oxide formation at the bonding interface.

Abstract translation: 在一个实施例中，用于半导体封装中的晶片到晶片结合的方法提供了使结合表面粗糙化的方法。 还提供了一种用于在接合期间被迫离开接合界面的较低熔点材料钝化接合表面的方法。 还提供了在键合界面处形成共晶的方法，以减少接合界面处的任何自然氧化物形成的影响。

公开(公告)号：US20230215851A1

公开(公告)日：2023-07-06

申请号：US17922139

申请日：2021-05-14

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhijun LV ,  Feng ZHANG ,  Wenqu LIU ,  Xiaoxin SONG ,  Zhao CUI ,  Liwen DONG ,  Detian MENG ,  Libo WANG ,  Dongfei HOU ,  Lizhen ZHANG

IPC: H01L25/16 ,  H01L27/12 ,  H01L33/00 ,  H01L23/00 ,  H01F7/20 ,  H01F7/06

CPC classification number: H01L25/167 ,  H01L27/124 ,  H01L33/0093 ,  H01L24/05 ,  H01L24/95 ,  H01F7/20 ,  H01F7/064 ,  H01L2224/05573 ,  H01L2224/06131 ,  H01L24/06 ,  H01L24/83 ,  H01L2224/2957 ,  H01L2224/29611 ,  H01L2224/29639 ,  H01L24/29 ,  H01L2224/83201 ,  H01L2224/95136 ,  H01L2224/95133

Abstract: A driving backplane, a transfer method for a light-emitting diode chip (21), and a display apparatus. The driving backplane comprises: a base substrate (10), a driving circuit, a plurality of electromagnetic structures (13), and a plurality of contact electrodes (12). The plurality of electromagnetic structures (13) in the driving backplane are symmetrically arranged relative to a first straight line (L1) and a second straight line (L2). A current signal can be applied to each electromagnetic structure (13) by means of the driving circuit. Stress generated by a transfer carrier plate (20) according to the magnetic force of each electromagnetic structure (13) moves the transfer carrier plate (20). When the transfer carrier plate (20) is stress balanced in each direction parallel to the surface of the transfer carrier plate (20), the light-emitting diode chip (21) is precisely aligned to corresponding contact electrodes (12).

公开(公告)号：US20160329259A1

公开(公告)日：2016-11-10

申请号：US15110907

申请日：2014-12-02

Applicant: ROBERT BOSCH GMBH

Inventor： Isabel Faria ,  Peter Pfeiffer ,  Heiko Elsinger ,  Andre Hahn

IPC: H01L23/29 ,  H01L23/00 ,  H01L21/56 ,  C09D183/04 ,  H01L23/31

CPC classification number: H01L23/295 ,  C08G77/12 ,  C08G77/20 ,  C08K2003/2227 ,  C08K2003/265 ,  C08K2003/267 ,  C08K2201/003 ,  C08K2201/005 ,  C09D183/04 ,  H01L21/563 ,  H01L23/26 ,  H01L23/296 ,  H01L23/3121 ,  H01L24/27 ,  H01L24/32 ,  H01L2224/29611 ,  H01L2224/32225 ,  H01L2924/0002 ,  H01L2924/186 ,  C08L83/00 ,  H01L2924/00 ,  C08K3/26

Abstract: A circuit carrier. The circuit carrier has at least one electronic component, the electronic component being soldered to the circuit carrier, in particular with the aid of a flux. The circuit carrier has, in particular, an electrically insulating protective layer for anti-condensation, a surface of the circuit carrier being covered at least partially with the protective layer. The protective layer of the circuit carrier is formed by a silicon polymer layer designed to be activatable with the aid of ultraviolet radiation, the silicon polymer layer having filler particles distributed in the silicon polymer layer, in particular homogenously. At least a part of the filler particles or all filler particles have at least one salt of an alkaline earth metal.

Abstract translation: 电路载体。 电路载体具有至少一个电子部件，电子部件特别是借助焊剂焊接到电路载体上。 电路载体尤其具有用于防冷凝的电绝缘保护层，电路载体的表面至少部分被保护层覆盖。 电路载体的保护层由设计成借助紫外线辐射激活的硅聚合物层形成，硅聚合物层具有分布在硅聚合物层中的填料颗粒，特别是均匀的。 至少一部分填料颗粒或所有填料颗粒具有至少一种碱土金属的盐。

公开(公告)号：US08975105B2

公开(公告)日：2015-03-10

申请号：US13163935

申请日：2011-06-20

Applicant: Cody B. Moody

Inventor： Cody B. Moody

IPC: H01L21/00 ,  H01L21/30 ,  H01L21/46 ,  H01L23/10 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L24/83 ,  H01L21/563 ,  H01L23/10 ,  H01L24/03 ,  H01L24/09 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/26135 ,  H01L2224/29023 ,  H01L2224/29035 ,  H01L2224/29562 ,  H01L2224/2957 ,  H01L2224/29609 ,  H01L2224/29611 ,  H01L2224/29624 ,  H01L2224/29644 ,  H01L2224/29686 ,  H01L2224/32055 ,  H01L2224/32148 ,  H01L2224/32502 ,  H01L2224/32506 ,  H01L2224/83054 ,  H01L2224/8309 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2224/83825 ,  H01L2224/83948 ,  H01L2224/94 ,  H01L2924/01032 ,  H01L2924/01322 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring.

Abstract translation: 密封的半导体晶片封装，其包括在第一晶片上的第一结合环，其面向第二晶片上的第二结合环的互补表面。 该封装包括形成在第一结合环的表面上的第一材料的第一和第二间隔，第一和第二间隔具有第一厚度。 该封装还包括共晶合金（不一定是共晶的，通常它是一种不是特定于元素的共晶比的合金），由第二种材料形成，并且第一种材料在第一和第二种之间形成气密封 晶片，通过将第一和第二晶片加热到高于第二材料的回流温度并低于第一材料的回流温度的温度而形成的共晶合金，其中共晶合金填充第一和第二间隙之间的体积， 和第二结合环，并且其中所述支架在所述第一结合环和所述第二结合环之间保持预定的距离。

公开(公告)号：US20090008804A1

公开(公告)日：2009-01-08

申请号：US12283204

申请日：2008-09-10

Applicant: Martin Standing ,  Robert J. Clarke

Inventor： Martin Standing ,  Robert J. Clarke

IPC: H01L23/28

CPC classification number: H01L24/33 ,  H01L23/296 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/4951 ,  H01L23/49562 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/41725 ,  H01L29/4232 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29611 ,  H01L2224/29644 ,  H01L2224/2969 ,  H01L2224/81054 ,  H01L2224/8121 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0715 ,  H01L2924/1032 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/29075 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A power semiconductor package that includes a semiconductor die having at least two power electrodes and a conductive clip electrically and mechanically coupled to each power electrode.

Abstract translation: 一种功率半导体封装，其包括具有至少两个功率电极的半导体管芯和与每个功率电极电气和机械耦合的导电夹子。

公开(公告)号：US20230253350A1

公开(公告)日：2023-08-10

申请号：US18186658

申请日：2023-03-20

Applicant: VueReal Inc.

Inventor： Gholamreza Chaji ,  Bahareh Sadeghimakki

IPC: H01L23/00 ,  H01L33/62

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/80 ,  H01L24/83 ,  H01L24/29 ,  H01L33/62 ,  H01L24/08 ,  H01L24/27 ,  H01L24/32 ,  H01L2224/80805 ,  H01L2224/03614 ,  H01L2224/0363 ,  H01L2224/05557 ,  H01L2224/08225 ,  H01L2224/32227 ,  H01L2224/29339 ,  H01L2224/29609 ,  H01L2224/80897 ,  H01L2224/83193 ,  H01L2224/03632 ,  H01L2224/29019 ,  H01L2224/29639 ,  H01L2224/04026 ,  H01L2224/27632 ,  H01L2224/29611 ,  H01L2224/2919 ,  H01L2224/29386 ,  H01L2224/29005 ,  H01L2224/056 ,  H01L2224/2957 ,  H01L2224/27614 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/05558 ,  H01L2224/29439 ,  H03H3/00

Abstract: This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.

公开(公告)号：US09754850B2

公开(公告)日：2017-09-05

申请号：US15110907

申请日：2014-12-02

Applicant: Robert Bosch GmbH

Inventor： Isabel Faria ,  Peter Pfeiffer ,  Heiko Elsinger ,  Andre Hahn

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  C09D183/04 ,  H01L23/26 ,  C08G77/12 ,  C08G77/20 ,  C08K3/22 ,  C08K3/26

CPC classification number: H01L23/295 ,  C08G77/12 ,  C08G77/20 ,  C08K2003/2227 ,  C08K2003/265 ,  C08K2003/267 ,  C08K2201/003 ,  C08K2201/005 ,  C09D183/04 ,  H01L21/563 ,  H01L23/26 ,  H01L23/296 ,  H01L23/3121 ,  H01L24/27 ,  H01L24/32 ,  H01L2224/29611 ,  H01L2224/32225 ,  H01L2924/0002 ,  H01L2924/186 ,  C08L83/00 ,  H01L2924/00 ,  C08K3/26

Abstract: A circuit carrier. The circuit carrier has at least one electronic component, the electronic component being soldered to the circuit carrier, in particular with the aid of a flux. The circuit carrier has, in particular, an electrically insulating protective layer for anti-condensation, a surface of the circuit carrier being covered at least partially with the protective layer. The protective layer of the circuit carrier is formed by a silicon polymer layer designed to be activatable with the aid of ultraviolet radiation, the silicon polymer layer having filler particles distributed in the silicon polymer layer, in particular homogenously. At least a part of the filler particles or all filler particles have at least one salt of an alkaline earth metal.

公开(公告)号：US09373609B2

公开(公告)日：2016-06-21

申请号：US13655228

申请日：2012-10-18

Applicant: Infineon Technologies AG

Inventor： Meng Tong Ong ,  Thiam Huat Lim ,  Kok Chai Goh

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/00 ,  H01L25/07 ,  H01L25/16 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/78 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/92 ,  H01L24/96 ,  H01L25/072 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/11003 ,  H01L2224/1112 ,  H01L2224/114 ,  H01L2224/1161 ,  H01L2224/11826 ,  H01L2224/13006 ,  H01L2224/13019 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/13171 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/13618 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13669 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/27003 ,  H01L2224/2712 ,  H01L2224/274 ,  H01L2224/2761 ,  H01L2224/27826 ,  H01L2224/28105 ,  H01L2224/29006 ,  H01L2224/29019 ,  H01L2224/29155 ,  H01L2224/29157 ,  H01L2224/2916 ,  H01L2224/29171 ,  H01L2224/29562 ,  H01L2224/2957 ,  H01L2224/29611 ,  H01L2224/29618 ,  H01L2224/29639 ,  H01L2224/29644 ,  H01L2224/29655 ,  H01L2224/29669 ,  H01L2224/3003 ,  H01L2224/30181 ,  H01L2224/30505 ,  H01L2224/92133 ,  H01L2224/92135 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/82

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip and a bump. The semiconductor chip has a contact pad on a major surface. The bump is disposed on the contact pad of the semiconductor chip. A solder layer is disposed on sidewalls of the bump.

Abstract translation: 根据本发明的实施例，半导体封装包括半导体芯片和凸块。 半导体芯片在主表面上具有接触焊盘。 凸块设置在半导体芯片的接触焊盘上。 焊料层设置在凸块的侧壁上。