公开(公告)号：US20140110835A1

公开(公告)日：2014-04-24

申请号：US13655228

申请日：2012-10-18

申请人： INFINEON TECHNOLOGIES AG

发明人： Meng Tong Ong ,  Thiam Huat Lim ,  Kok Chai Goh

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L25/50 ,  H01L21/78 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/92 ,  H01L24/96 ,  H01L25/072 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/11003 ,  H01L2224/1112 ,  H01L2224/114 ,  H01L2224/1161 ,  H01L2224/11826 ,  H01L2224/13006 ,  H01L2224/13019 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/13171 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/13618 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13669 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/27003 ,  H01L2224/2712 ,  H01L2224/274 ,  H01L2224/2761 ,  H01L2224/27826 ,  H01L2224/28105 ,  H01L2224/29006 ,  H01L2224/29019 ,  H01L2224/29155 ,  H01L2224/29157 ,  H01L2224/2916 ,  H01L2224/29171 ,  H01L2224/29562 ,  H01L2224/2957 ,  H01L2224/29611 ,  H01L2224/29618 ,  H01L2224/29639 ,  H01L2224/29644 ,  H01L2224/29655 ,  H01L2224/29669 ,  H01L2224/3003 ,  H01L2224/30181 ,  H01L2224/30505 ,  H01L2224/92133 ,  H01L2224/92135 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/82

摘要： In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip and a bump. The semiconductor chip has a contact pad on a major surface. The bump is disposed on the contact pad of the semiconductor chip. A solder layer is disposed on sidewalls of the bump.

摘要翻译： 根据本发明的实施例，半导体封装包括半导体芯片和凸块。 半导体芯片在主表面上具有接触焊盘。 凸块设置在半导体芯片的接触焊盘上。 焊料层设置在凸块的侧壁上。

公开(公告)号：US20090115042A1

公开(公告)日：2009-05-07

申请号：US11570009

申请日：2005-06-03

申请人： Mitsumasa Koyanagi

发明人： Mitsumasa Koyanagi

IPC分类号： H01L23/00 ,  H01L21/00

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3135 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/12105 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/13609 ,  H01L2224/13644 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14505 ,  H01L2224/14515 ,  H01L2224/1703 ,  H01L2224/17505 ,  H01L2224/17515 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81097 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81201 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/83007 ,  H01L2224/83101 ,  H01L2224/83193 ,  H01L2224/83825 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92125 ,  H01L2224/92133 ,  H01L2224/92135 ,  H01L2224/92224 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2224/45111 ,  H01L2924/01014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A three-dimensional stacked structured semiconductor device comprising semiconductor circuit layers stacked on a support substrate, and a method of fabricating the device are provided.After fixing semiconductor chips 37 to a support substrate 31 with bump electrodes, gaps between the chips 37 are filled with an electrically insulative adhesive 38. Then, by polishing the reverses of the chips 37, the chips 37 are thinned to expose buried interconnections in the chips 37, thereby forming a first semiconductor circuit layer L1. Next, after fixing semiconductor chips 43 to the first semiconductor circuit layer L1 with bump electrodes 41 and 42 by way of an insulating layer 39, gaps between the chips 43 are filled with an electrically insulative adhesive 44. Then, by polishing the reverses of the chips 43, the chips 43 are thinned to expose buried interconnections in the chips 43, thereby forming a second semiconductor circuit layer L2. In a similar way, semiconductor chips 49 are fixed to the second semiconductor circuit layer L2 by way of an insulating layer 45, thereby forming a third semiconductor circuit layer L3. Dicing is performed as necessary. Thus, three-layer stacked structured semiconductor devices 30A, 30B, and 30C are obtained.

摘要翻译： 提供了一种包括堆叠在支撑衬底上的半导体电路层的三维堆叠结构的半导体器件及其制造方法。 在将半导体芯片37固定到具有凸块电极的支撑基板31上之后，用电绝缘粘合剂38填充芯片37之间的间隙。然后，通过抛光芯片37的反向，使芯片37变薄以暴露出掩模互连 芯片37，从而形成第一半导体电路层L1。 接下来，在通过绝缘层39将半导体芯片43固定到具有凸块电极41和42的第一半导体电路层L1之后，用电绝缘粘合剂44填充芯片43之间的间隙。然后，通过抛光 芯片43，芯片43变薄以暴露芯片43中的掩埋互连，从而形成第二半导体电路层L2。 以类似的方式，通过绝缘层45将半导体芯片49固定到第二半导体电路层L2，从而形成第三半导体电路层L3。 根据需要进行切割。 因此，获得三层堆叠结构的半导体器件30A，30B和30C。

公开(公告)号：US09373609B2

公开(公告)日：2016-06-21

申请号：US13655228

申请日：2012-10-18

申请人： Infineon Technologies AG

发明人： Meng Tong Ong ,  Thiam Huat Lim ,  Kok Chai Goh

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/00 ,  H01L25/07 ,  H01L25/16 ,  H01L21/78 ,  H01L23/00

CPC分类号： H01L25/50 ,  H01L21/78 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/92 ,  H01L24/96 ,  H01L25/072 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/11003 ,  H01L2224/1112 ,  H01L2224/114 ,  H01L2224/1161 ,  H01L2224/11826 ,  H01L2224/13006 ,  H01L2224/13019 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/13171 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/13618 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13669 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/27003 ,  H01L2224/2712 ,  H01L2224/274 ,  H01L2224/2761 ,  H01L2224/27826 ,  H01L2224/28105 ,  H01L2224/29006 ,  H01L2224/29019 ,  H01L2224/29155 ,  H01L2224/29157 ,  H01L2224/2916 ,  H01L2224/29171 ,  H01L2224/29562 ,  H01L2224/2957 ,  H01L2224/29611 ,  H01L2224/29618 ,  H01L2224/29639 ,  H01L2224/29644 ,  H01L2224/29655 ,  H01L2224/29669 ,  H01L2224/3003 ,  H01L2224/30181 ,  H01L2224/30505 ,  H01L2224/92133 ,  H01L2224/92135 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/82

摘要： In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip and a bump. The semiconductor chip has a contact pad on a major surface. The bump is disposed on the contact pad of the semiconductor chip. A solder layer is disposed on sidewalls of the bump.

摘要翻译： 根据本发明的实施例，半导体封装包括半导体芯片和凸块。 半导体芯片在主表面上具有接触焊盘。 凸块设置在半导体芯片的接触焊盘上。 焊料层设置在凸块的侧壁上。

公开(公告)号：US09343439B2

公开(公告)日：2016-05-17

申请号：US14884864

申请日：2015-10-16

申请人： SK hynix Inc.

发明人： Jin Ho Bae ,  Han Jun Bae

IPC分类号： H01L23/48 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/92135 ,  H01L2224/92164 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06568 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. A second chip is stacked on the first chip to expose outer portions of the first connectors. The second chip has second connectors on edges thereof. Connection members to connect the exposed outer portions of the first connectors to the connection terminals. Sidewall interconnectors to connect the exposed outer portions of the first connectors to the second connectors. The sidewall interconnectors extend from the exposed outer portions of the first connectors along sidewalls of the second chip to cover the second connectors.

公开(公告)号：US12051655B2

公开(公告)日：2024-07-30

申请号：US17377387

申请日：2021-07-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jen-Jui Yu ,  Ching-Hua Hsieh ,  Cheng-Ting Chen ,  Hsiu-Jen Lin ,  Wei-Yu Chen ,  Chih-Chiang Tsao ,  Chao-Wei Chiu

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L25/16

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/6836 ,  H01L24/16 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/16 ,  H01L2221/68331 ,  H01L2224/16265 ,  H01L2224/214 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24155 ,  H01L2224/24265 ,  H01L2224/25171 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32265 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/81024 ,  H01L2224/81815 ,  H01L2224/9211 ,  H01L2224/92133 ,  H01L2224/92135 ,  H01L2924/1815 ,  H01L2924/19011 ,  H01L2924/19104

摘要： A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a redistribution layer (RDL) structure, a passive device, and a plurality of dummy items. The encapsulant laterally encapsulates the die. The RDL structure is disposed on the die and the encapsulant. The passive device is disposed on and electrically bonded to the RDL structure. The plurality of dummy items are disposed on the RDL structure and laterally aside the passive device, wherein top surfaces of the plurality of dummy items are higher than a top surface of the passive device.

公开(公告)号：US11854922B2

公开(公告)日：2023-12-26

申请号：US17353805

申请日：2021-06-21

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Joseph Liu

IPC分类号： H01L23/31 ,  H01L23/00

CPC分类号： H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L24/02 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/0233 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/221 ,  H01L2224/244 ,  H01L2224/24137 ,  H01L2224/24155 ,  H01L2224/32137 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/92135 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104

摘要： A semiconductor package includes a semiconductor substrate forming a cavity and a redistribution layer on a first side of the semiconductor substrate, the redistribution layer forming die contacts within the cavity and a set of terminals for the semiconductor package opposite the semiconductor substrate. The redistribution layer electrically connects one or more of the die contacts to the set of terminals. The semiconductor package further includes a semiconductor die including die terminals within the cavity with the die terminals electrically coupled to the die contacts within the cavity.

公开(公告)号：US20080318054A1

公开(公告)日：2008-12-25

申请号：US11766340

申请日：2007-06-21

申请人： Raymond Albert Fillion ,  Ryan Christopher Mills

发明人： Raymond Albert Fillion ,  Ryan Christopher Mills

IPC分类号： B32B27/36 ,  B32B9/04 ,  H01L23/58

CPC分类号： H01L24/20 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L24/97 ,  H01L24/98 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05082 ,  H01L2224/051 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/20 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/2919 ,  H01L2224/32221 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92135 ,  H01L2224/92144 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  Y10T428/31507 ,  H01L2924/014 ,  H01L2224/19 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/0105

摘要： An electronic component includes a base insulative layer having a first surface and a second surface; an electronic device having a first surface and a second surface, and the electronic device being secured to the base insulative layer; an adhesive layer disposed between the first surface of the electronic device and the second surface of the base insulative layer; and a removable layer disposed between the first surface of the electronic device and the second surface of the base insulative layer. The base insulative layer secures to the electronic device through the removable layer. The removable layer releases the base insulative layer from the electronic device at a sufficiently low temperature.

摘要翻译： 电子部件包括具有第一表面和第二表面的基底绝缘层; 具有第一表面和第二表面的电子设备，并且所述电子设备固定到所述基底绝缘层; 设置在电子设备的第一表面和基底绝缘层的第二表面之间的粘合剂层; 以及设置在电子设备的第一表面和基底绝缘层的第二表面之间的可移除层。 基底绝缘层通过可移除层固定到电子设备。 可去除层在足够低的温度下从电子器件释放基极绝缘层。

公开(公告)号：US20080318413A1

公开(公告)日：2008-12-25

申请号：US11766302

申请日：2007-06-21

申请人： Raymond Albert Fillion ,  David Richard Esler ,  Jeffrey Scott Erlbaum ,  Ryan Christopher Mills ,  Charles Gerard Woychik

发明人： Raymond Albert Fillion ,  David Richard Esler ,  Jeffrey Scott Erlbaum ,  Ryan Christopher Mills ,  Charles Gerard Woychik

IPC分类号： H01L21/4763

CPC分类号： H01L24/19 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/20 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L24/97 ,  H01L24/98 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05082 ,  H01L2224/051 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/20 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/2919 ,  H01L2224/32221 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/83132 ,  H01L2224/8385 ,  H01L2224/92135 ,  H01L2224/92144 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2224/19 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/014

摘要： A method is provided for making an interconnect structure. The method includes applying a removable layer to an electronic device or to a base insulative layer; applying an adhesive layer to the electronic device or to the base insulative layer; and securing the electronic device to the base insulative layer using the adhesive layer.

摘要翻译： 提供了一种制造互连结构的方法。 该方法包括将可移除层应用于电子设备或基底绝缘层; 将粘合剂层施加到电子装置或基底绝缘层上; 以及使用所述粘合剂层将所述电子器件固定到所述基底绝缘层。

公开(公告)号：US07262444B2

公开(公告)日：2007-08-28

申请号：US11205903

申请日：2005-08-17

申请人： Raymond Albert Fillion ,  Richard Alfred Beaupre ,  Ahmed Elasser ,  Robert John Wojnarowski ,  Charles Steven Korman

发明人： Raymond Albert Fillion ,  Richard Alfred Beaupre ,  Ahmed Elasser ,  Robert John Wojnarowski ,  Charles Steven Korman

IPC分类号： H01L31/111 ,  H01L21/48

CPC分类号： H01L23/4822 ,  H01L23/4821 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/072 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92135 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor chip packaging structure comprising a dielectric film having one or more through holes aligned with the one or more contact pads of at least one power semiconductor chip. A patterned electrically conductive layer adjacent to the dielectric film has one or more electrically conductive posts which extend through the one or more though holes aligned with the contact pads to electrically couple the conductive layer to the contact pads. In certain embodiments, one or more air gaps may be formed between the dielectric film and the active surface of the at least one power semiconductor chip. Methods for fabricating the semiconductor chip packaging structure are also disclosed.

摘要翻译： 一种半导体芯片封装结构，包括具有与至少一个功率半导体芯片的一个或多个接触焊盘对准的一个或多个通孔的电介质膜。 与电介质膜相邻的图案化导电层具有一个或多个导电柱，其延伸穿过与接触焊盘对准的一个或多个通孔，以将导电层电耦合到接触焊盘。 在某些实施例中，可以在介电膜和至少一个功率半导体芯片的有源表面之间形成一个或多个气隙。 还公开了制造半导体芯片封装结构的方法。

公开(公告)号：US20070040186A1

公开(公告)日：2007-02-22

申请号：US11205903

申请日：2005-08-17

申请人： Raymond Fillion ,  Richard Beaupre ,  Ahmed Elasser ,  Robert Wojnarowski ,  Charles Korman

发明人： Raymond Fillion ,  Richard Beaupre ,  Ahmed Elasser ,  Robert Wojnarowski ,  Charles Korman

IPC分类号： H01L31/111 ,  H01L21/48

CPC分类号： H01L23/4822 ,  H01L23/4821 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/072 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92135 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor chip packaging structure comprising a dielectric film having one or more through holes aligned with the one or more contact pads of at least one power semiconductor chip. A patterned electrically conductive layer adjacent to the dielectric film has one or more electrically conductive posts which extend through the one or more though holes aligned with the contact pads to electrically couple the conductive layer to the contact pads. In certain embodiments, one or more air gaps may be formed between the dielectric film and the active surface of the at least one power semiconductor chip. Methods for fabricating the semiconductor chip packaging structure are also disclosed.