公开(公告)号：US09859200B2

公开(公告)日：2018-01-02

申请号：US14792447

申请日：2015-07-06

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： SooSan Park ,  KyuSang Kim ,  YeoChan Ko ,  KeoChang Lee ,  HeeJo Chi ,  HeeSoo Lee

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/482 ,  H01L21/56 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49833 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/4828 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83104 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15331 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a base substrate, the base substrate includes a base terminal; an integrated circuit device on the base substrate; a bottom conductive joint on the base terminal; a conductive ball on the bottom conductive joint, the conductive ball includes a core body; and an interposer over the conductive ball.

公开(公告)号：US09748157B1

公开(公告)日：2017-08-29

申请号：US13904401

申请日：2013-05-29

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： HeeJo Chi ,  HanGil Shin ,  NamJu Cho ,  Kyung Moon Kim

IPC: H01L23/00 ,  H01L23/28 ,  H01L21/56

CPC classification number: H01L23/28 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/00

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a base substrate having a bottom pad; an integrated circuit device mounted on the base substrate; an interposer having a package interconnect mounted on the base substrate, the package interconnect includes an underside base portion having an irregular surface characteristic of a coining process; and an encapsulation between the interposer and the base substrate.

公开(公告)号：US20180108542A1

公开(公告)日：2018-04-19

申请号：US15846014

申请日：2017-12-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo ,  HeeJo Chi

IPC: H01L21/56

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48158 ,  H01L2224/4816 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81001 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.

公开(公告)号：US09679769B1

公开(公告)日：2017-06-13

申请号：US15199751

申请日：2016-06-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Zigmund Ramirez Camacho ,  Bartholomew Liao Chung Foh ,  Sheila Marie L. Alvarez ,  Dao Nguyen Phu Cuong ,  HeeJo Chi

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/12 ,  H01L23/485 ,  H01L21/033 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/0335 ,  H01L21/485 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/76879 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/53242 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05026 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a photoimagable dielectric layer having a trace opening for exposing the carrier; a trace within the trace opening; an inner solder resist layer directly on the photoimagable dielectric layer and the trace, the inner solder resist layer having a bond pad opening for exposing the trace; an integrated circuit over the inner solder resist layer, the integrated circuit electrically connected to the trace through the bond pad opening; an encapsulation directly on the integrated circuit and the inner solder resist layer; and an external interconnect electrically coupled to the trace and the integrated circuit.

公开(公告)号：US10573600B2

公开(公告)日：2020-02-25

申请号：US15649491

申请日：2017-07-13

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： HeeJo Chi ,  NamJu Cho ,  JunWoo Myung

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H05K1/18 ,  H01L23/31 ,  H01L23/367 ,  H05K3/00 ,  H05K3/42

Abstract: A semiconductor device has a first semiconductor die stacked over a second semiconductor die which is mounted to a temporary carrier. A plurality of bumps is formed over an active surface of the first semiconductor die around a perimeter of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. A plurality of conductive vias is formed through the encapsulant around the first and second semiconductor die. A portion of the encapsulant and a portion of a back surface of the first and second semiconductor die is removed. An interconnect structure is formed over the encapsulant and the back surface of the first or second semiconductor die. The interconnect structure is electrically connected to the conductive vias. The carrier is removed. A heat sink or shielding layer can be formed over the encapsulant and first semiconductor die.

公开(公告)号：US09865575B2

公开(公告)日：2018-01-09

申请号：US15202349

申请日：2016-07-05

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： HeeJo Chi ,  HanGil Shin ,  KyungMoon Kim

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/831 ,  H01L2224/8385 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods of forming conductive and insulating layers for semiconductor devices and packages. Substrate is provided with integrated circuit device and interconnect structure mounted thereon, the interconnect structure adjacent the integrated circuit device. The integrated circuit device and portions of the interconnect structure can be covered with an encapsulation exposing a portion of the interconnect structure. Conductive material is formed over the exposed portion of the interconnect structure by a depositing process followed by a heating process to alter the chemical properties of the conductive material. Optionally, a dispersing process may be incorporated.

公开(公告)号：US09865554B2

公开(公告)日：2018-01-09

申请号：US14955033

申请日：2015-11-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Il Kwon Shim ,  Kyung Moon Kim ,  HeeJo Chi ,  JunMo Koo ,  Bartholomew Liao Chung Foh ,  Zigmund Ramirez Camacho

IPC: H01L21/60 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03001 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/039 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05664 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/01074 ,  H01L2224/05164 ,  H01L2224/05644 ,  H01L2224/3318

Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming a protection layer on top of the contact pads and the substrate; exposing the contact pads from the protection layer; printing under bump metallization (UBM) layers over the exposed contact pads extended over the protection layer with conductive inks; and forming bumps on top of the under bump metallization layers. It also including: printing an adhesion layer using conductive ink, wherein the adhesion layer comprises interconnected adhesion layer pads; forming additional under bump metallization (UBM) layers and bumps on top of the adhesion layer pads utilizing an electro-deposition process; and removing connections among the interconnected adhesion layer pads.

公开(公告)号：US20170250154A1

公开(公告)日：2017-08-31

申请号：US15594443

申请日：2017-05-12

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： HeeJo Chi ,  HanGil Shin ,  NamJu Cho

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L24/19 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/08235 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/19 ,  H01L2224/24227 ,  H01L2224/25171 ,  H01L2224/82039 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/153 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2224/08

Abstract: A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure.

公开(公告)号：US11688612B2

公开(公告)日：2023-06-27

申请号：US15846014

申请日：2017-12-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo ,  HeeJo Chi

IPC: H01L21/56 ,  H01L21/683 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L23/552

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/05552 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/4816 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48158 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81001 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00014 ,  H01L2924/0103 ,  H01L2924/014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/0105 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/1532 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/3025 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/97 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/1306 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/0002 ,  H01L2224/05552 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.

公开(公告)号：US10510703B2

公开(公告)日：2019-12-17

申请号：US15594443

申请日：2017-05-12

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： HeeJo Chi ,  HanGil Shin ,  NamJu Cho

IPC: H01L23/00 ,  H01L23/528 ,  H01L21/768 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L23/538 ,  H01L21/683

Abstract: A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure.