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    Semiconductor device and method of balancing surfaces of an embedded PCB unit with a dummy copper pattern
    5.
    发明授权
    Semiconductor device and method of balancing surfaces of an embedded PCB unit with a dummy copper pattern 有权

    公开(公告)号：US10177010B2

    公开(公告)日：2019-01-08

    申请号：US15235008

    申请日：2016-08-11

    申请人： STATS ChipPAC Pte. Ltd.

    发明人： Yaojian Lin ,  Kang Chen ,  Hin Hwa Goh ,  Il Kwon Shim

    IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L23/13 ,  H01L23/538

    摘要： A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.

    Double-sided semiconductor package and dual-mold method of making same
    6.
    发明授权
    Double-sided semiconductor package and dual-mold method of making same 有权

    公开(公告)号：US10115672B2

    公开(公告)日：2018-10-30

    申请号：US15816743

    申请日：2017-11-17

    申请人： STATS ChipPAC Pte. Ltd.

    发明人： Il Kwon Shim ,  Pandi C. Marimuthu ,  Yaojian Lin

    IPC分类号： H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L21/48 ,  H01L25/16

    摘要： A semiconductor device comprises a first conductive layer formed on a carrier over an insulating layer. A portion of the insulating layer is removed prior to forming the first conductive layer. A first semiconductor die is disposed over the first conductive layer. A discrete electrical component is disposed over the first conductive layer adjacent to the first semiconductor die. A first encapsulant is deposited over the first conductive layer and first semiconductor layer. A conductive pillar is formed through the first encapsulant between the first conductive layer and second conductive layer. A second encapsulant is deposited around the first encapsulant, first conductive layer, and first semiconductor die. A second conductive layer is formed over the first semiconductor die, first encapsulant, and second encapsulant opposite the first conductive layer. The carrier is removed after forming the second conductive layer. A semiconductor package is mounted to the first conductive layer.

    Semiconductor Device and Method of Forming Embedded Wafer Level Chip Scale Packages
    10.
    发明申请
    Semiconductor Device and Method of Forming Embedded Wafer Level Chip Scale Packages 有权

    公开(公告)号：US20230012958A1

    公开(公告)日：2023-01-19

    申请号：US17936714

    申请日：2022-09-29

    申请人： STATS ChipPAC Pte. Ltd.

    发明人： Yaojian Lin ,  Pandi C. Marimuthu ,  Il Kwon Shim ,  Byung Joon Han

    IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/786 ,  H01L21/784 ,  H01L21/782 ,  H01L21/82 ,  H01L21/78

    摘要： A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less.