公开(公告)号：US09679769B1

公开(公告)日：2017-06-13

申请号：US15199751

申请日：2016-06-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Zigmund Ramirez Camacho ,  Bartholomew Liao Chung Foh ,  Sheila Marie L. Alvarez ,  Dao Nguyen Phu Cuong ,  HeeJo Chi

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/12 ,  H01L23/485 ,  H01L21/033 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/0335 ,  H01L21/485 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/76879 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/53242 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05026 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a photoimagable dielectric layer having a trace opening for exposing the carrier; a trace within the trace opening; an inner solder resist layer directly on the photoimagable dielectric layer and the trace, the inner solder resist layer having a bond pad opening for exposing the trace; an integrated circuit over the inner solder resist layer, the integrated circuit electrically connected to the trace through the bond pad opening; an encapsulation directly on the integrated circuit and the inner solder resist layer; and an external interconnect electrically coupled to the trace and the integrated circuit.

公开(公告)号：US09659897B1

公开(公告)日：2017-05-23

申请号：US15167895

申请日：2016-05-27

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Zigmund Ramirez Camacho ,  Emmanuel Espiritu ,  Bartholomew Liao Chung Foh ,  Dao Nguyen Phu Cuong ,  Jeffrey David Punzalan

IPC: H01L23/22 ,  H01L23/24 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L24/25 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/562 ,  H01L24/17 ,  H01L25/04 ,  H01L2224/16225 ,  H01L2224/1701 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: A system and a method of manufacture thereof of integrated circuit packaging system, including: a pillar; a conductive buildup attached to the pillar; and a molded body encapsulating the conductive buildup, the pillar extending out of the molded body.

公开(公告)号：US09865554B2

公开(公告)日：2018-01-09

申请号：US14955033

申请日：2015-11-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Il Kwon Shim ,  Kyung Moon Kim ,  HeeJo Chi ,  JunMo Koo ,  Bartholomew Liao Chung Foh ,  Zigmund Ramirez Camacho

IPC: H01L21/60 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03001 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/039 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05664 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/01074 ,  H01L2224/05164 ,  H01L2224/05644 ,  H01L2224/3318

Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming a protection layer on top of the contact pads and the substrate; exposing the contact pads from the protection layer; printing under bump metallization (UBM) layers over the exposed contact pads extended over the protection layer with conductive inks; and forming bumps on top of the under bump metallization layers. It also including: printing an adhesion layer using conductive ink, wherein the adhesion layer comprises interconnected adhesion layer pads; forming additional under bump metallization (UBM) layers and bumps on top of the adhesion layer pads utilizing an electro-deposition process; and removing connections among the interconnected adhesion layer pads.

公开(公告)号：US10109587B1

公开(公告)日：2018-10-23

申请号：US15226735

申请日：2016-08-02

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Dao Nguyen Phu Cuong ,  Bartholomew Liao Chung Foh ,  Byung Tai Do ,  Kyung Moon Kim ,  Jeffrey David Punzalan ,  SeungYong Chai ,  Soo Won Lee ,  Kwok Keung Szeto ,  KyungOe Kim

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L21/768

Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.