公开(公告)号：US20160380119A1

公开(公告)日：2016-12-29

申请号：US15084874

申请日：2016-03-30

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Dong Yun JUNG ,  Hyun Soo LEE ,  Sang Choon KO ,  Jeong-Jin KIM ,  Zin-Sig KIM ,  Jeho NA ,  Eun Soo NAM ,  Jae Kyoung MUN ,  Young Rak PARK ,  Sung-Bum BAE ,  Hyung Seok LEE ,  Woojin CHANG ,  Hyungyu JANG ,  Chi Hoon JUN

IPC分类号： H01L29/872 ,  H01L29/205 ,  H01L29/45 ,  H01L21/02 ,  H01L23/29 ,  H01L29/47 ,  H01L29/66 ,  H01L21/306 ,  H01L29/20 ,  H01L23/31

CPC分类号： H01L21/0228 ,  H01L23/291 ,  H01L23/3178 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66212 ,  H01L29/872

摘要： A first nitride semiconductor layer of a semiconductor device is provided on a substrate, a second nitride semiconductor layer is provided on the first nitride semiconductor layer, a first ohmic metal and a second ohmic metal are provided on the second nitride semiconductor layer, a recess region is provided in the second nitride semiconductor layer between the first ohmic metal and the second ohmic metal, a passivation layer covers side of the first ohmic metal and a bottom surface and sides of the recess region, and a Schottky electrode is provided on the first ohmic metal and extends into the recess region.

摘要翻译： 半导体器件的第一氮化物半导体层设置在衬底上，第二氮化物半导体层设置在第一氮化物半导体层上，第一欧姆金属和第二欧姆金属设置在第二氮化物半导体层上，凹部 在所述第一欧姆金属和所述第二欧姆金属之间的所述第二氮化物半导体层中设置钝化层，所述钝化层覆盖所述第一欧姆金属的一侧，并且所述钝化层覆盖所述凹部区域的底表面和所述侧面，并且所述第一欧姆金属的肖特基电极 金属并延伸到凹陷区域中。

公开(公告)号：US20160020147A1

公开(公告)日：2016-01-21

申请号：US14862123

申请日：2015-09-22

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Jongmin LEE ,  Byoung-Gue MIN ,  Seong-il KIM ,  Hyung Sup YOON ,  Jae Kyoung MUN ,  Eun Soo NAM

IPC分类号： H01L21/8222 ,  H01L27/06

CPC分类号： H01L21/8222 ,  H01G7/00 ,  H01L27/0647 ,  H01L27/0658 ,  H01L29/93 ,  H03F1/565 ,  H03F3/21 ,  H03F2200/36 ,  H03F2200/378 ,  H03F2200/387 ,  H03F2200/391 ,  H03H7/38 ,  Y10T29/43

摘要： A manufacturing method for a variable capacitor includes forming a first element of which a capacitance value depends on a voltage applied to both of two terminals of a first area on a substrate, forming a second element having a capacitance value fixed to a second area on the substrate adjacent to the first area, and forming metallic wires for connecting the first element and the second element and connecting the first element and the second element with the outside. The first element maybe a bipolar transistor that may include a diode. The second element maybe a capacitor that includes a dielectric.

摘要翻译： 一种可变电容器的制造方法，包括：形成电容值取决于施加到基板上的第一区域的两端的电压的第一元件，形成具有固定在第二区域上的电容值的第二元件 基板，与第一区域相邻，并且形成用于连接第一元件和第二元件的金属线，并且将第一元件和第二元件与外部连接。 第一个元件可以是可以包括二极管的双极晶体管。 第二元件可以是包括电介质的电容器。

公开(公告)号：US20150194363A1

公开(公告)日：2015-07-09

申请号：US14324724

申请日：2014-07-07

申请人： Electronics and Telecommunications Research Institute

发明人： Chi Hoon JUN ,  Sang Choon KO ,  Seok-Hwan MOON ,  Woojin CHANG ,  Sung-Bum BAE ,  Young Rak PARK ,  Je Ho NA ,  Jae Kyoung MUN ,  Eun Soo NAM

IPC分类号： H01L23/367 ,  H01L21/3205 ,  H01L23/467 ,  H01L21/3065 ,  H01L21/308 ,  H01L23/473

CPC分类号： H01L21/3065 ,  H01L21/3081 ,  H01L21/32051 ,  H01L23/367 ,  H01L23/467 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括：设置在衬底上的有源区; 入口通道形成为隐藏在所述基板的一侧中的单个腔; 出口通道形成为埋在基板的另一侧中的单个腔; 微通道阵列，其包括多个微通道，其中所述多个微通道形成为埋在所述衬底中的多个空腔，并且所述微通道阵列的一端连接到所述入口通道的一侧，而另一端 的微通道阵列连接到出口通道的一侧; 以及将微通道彼此分离的微型散热器阵列。

公开(公告)号：US20140035044A1

公开(公告)日：2014-02-06

申请号：US14049816

申请日：2013-10-09

申请人： Electronics and Telecommunications Research Institute

发明人： Hokyun AHN ,  Jong-Won LIM ,  Hyung Sup YOON ,  Byoung-Gue MIN ,  Sang-Heung LEE ,  Hae Cheon KIM ,  Eun Soo NAM

IPC分类号： H01L29/78

CPC分类号： H01L29/7831 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/7787 ,  H01L29/812

摘要： Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.

摘要翻译： 公开了场效应晶体管及其制造方法。 所公开的场效应晶体管包括：半导体衬底; 源极欧姆金属层，形成在半导体衬底的一侧上; 形成在所述半导体衬底的另一侧上的漏极欧姆金属层; 在所述源极欧姆金属层和所述漏极欧姆金属层之间形成的栅电极，位于所述半导体衬底的上部; 形成在包括源极欧姆金属层，漏极欧姆金属层和栅电极的半导体衬底的上部上的绝缘膜; 以及形成在绝缘膜的上部的多个场电极，其中，各个场电极下方的绝缘膜具有不同的厚度。

公开(公告)号：US20150380482A1

公开(公告)日：2015-12-31

申请号：US14658121

申请日：2015-03-13

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Ho Kyun AHN ,  Hae Cheon KIM ,  Jong Won LIM ,  Dong Min KANG ,  Yong Hwan KWON ,  SEONG IL KIM ,  Zin Sig KIM ,  Eun Soo NAM ,  Byoung Gue MIN ,  Hyung Sup YOON ,  Kyung Ho LEE ,  Jong Min LEE ,  Kyu Jun CHO

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L21/28 ,  H01L29/49 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/31 ,  H01L29/778 ,  H01L29/45

CPC分类号： H01L21/28264 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7786

摘要： Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.

摘要翻译： 本文提供了包括基板的半导体器件; 形成在所述基板的顶部上的有源层; 形成在所述有源层的顶部上并具有第一孔的保护层; 源电极，形成在保护层顶部的驱动栅电极和漏电极; 以及形成在所述第一孔的顶部上的第一附加栅电极，其中由于施加到所述源电极，漏电极和驱动栅电极中的每一个的电压，向所述有源层，保护层和驱动栅电极施加电场， 并且第一附加栅电极被配置为衰减施加到有源层，保护层和驱动栅电极的至少一部分的电场的尺寸。

公开(公告)号：US20150380354A1

公开(公告)日：2015-12-31

申请号：US14845435

申请日：2015-09-04

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Byoung-Gue MIN ,  Sang Choon KO ,  Jong-Won LIM ,  Hokyun AHN ,  Hyung Sup YOON ,  Jae Kyoung MUN ,  Eun Soo NAM

IPC分类号： H01L23/535 ,  H01L23/48

CPC分类号： H01L23/535 ,  H01L21/02365 ,  H01L21/28 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

摘要翻译： 半导体器件可以包括具有下通孔的衬底，具有暴露衬底的顶表面的开口的外延层，设置在衬底的顶表面上并包括第一，第二和第三电极的半导体芯片， 连接到第一电极的上金属层，设置在上金属层上并具有上通孔的支撑基板，设置在基板上并延伸到上通孔中的上焊盘，连接到第二电极的下焊盘 以及覆盖基板的底面的下金属层，并且通过下通路孔与下焊盘连接。

公开(公告)号：US20150194494A1

公开(公告)日：2015-07-09

申请号：US14243322

申请日：2014-04-02

申请人： Electronics and Telecommunications Research Institute

发明人： Ho Kyun AHN ,  Hae Cheon KIM ,  Zin Sig KIM ,  Sang Heung LEE ,  Byoung Gue MIN ,  Hyung Sup YOON ,  Dong Min KANG ,  Seong Il KIM ,  Jong Min LEE ,  Jong Won LIM ,  Yong Hwan KWON ,  Eun Soo NAM

IPC分类号： H01L29/40 ,  H01L29/66 ,  H01L21/28 ,  H01L21/283 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/402 ,  H01L21/283 ,  H01L21/28593 ,  H01L29/2003 ,  H01L29/42312 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/7787

摘要： Disclosed are a field effect transistor for high voltage driving including a gate electrode structure in which a gate head extended in a direction of a drain is supported by a field plate embedded under a region of the gate head so as to achieve high voltage driving, and a manufacturing method thereof. Accordingly, the gate head extended in the direction of the drain is supported by the field plate electrically spaced by using an insulating layer, so that it is possible to stably manufacture a gate electrode including the extended gate head, and gate resistance is decreased by the gate head extended in the direction of the drain and an electric field peak value between the gate and the drain is decreased by the gate electrode including the gate head extended in the direction of the drain and the field plate proximate to the gate, thereby achieving an effect in that a breakdown voltage of a device is increased.

摘要翻译： 公开了一种用于高电压驱动的场效应晶体管，其包括栅极电极结构，其中在漏极方向上延伸的栅极头由嵌入在栅极头的区域内的场板支撑以实现高电压驱动，以及 其制造方法。 因此，在漏极方向上延伸的栅极头通过使用绝缘层而被电隔离的场板支撑，使得可以稳定地制造包括延伸栅极头的栅电极，并且栅极电阻通过 栅极头在漏极的方向上延伸，栅极和漏极之间的电场峰值由包括在漏极方向上延伸的栅极和靠近栅极的场板的栅电极减小，由此实现 效果是器件的击穿电压增加。

公开(公告)号：US20150079722A1

公开(公告)日：2015-03-19

申请号：US14553968

申请日：2014-11-25

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Bongki MHEEN ,  Myoungsook OH ,  Kisoo KIM ,  Jae-Sik SIM ,  Yong-Hwan KWON ,  Eun Soo NAM

IPC分类号： H01L31/18 ,  H01L31/0352 ,  H01L31/107

CPC分类号： H01L31/18 ,  H01L31/02002 ,  H01L31/035272 ,  H01L31/107

摘要： Disclosed are an avalanche photodiode with a guard ring structure that relieves edge breakdown by an external voltage which is applied through a metal pad which is attached to the guard ring and a manufacturing method thereof. An avalanche photodiode with a guard ring structure includes a plurality of semiconductor layers laminated on a substrate; an active region partially formed above the semiconductor layers; a guard ring which is formed above the semiconductor layers and disposed so as to be spaced apart from the active region and have a ring shape that encloses the active region; and a connecting unit formed on the semiconductor layers to be electrically connected to the guard ring so as to apply an external voltage to the guard ring region. Therefore, the external voltage is applied to the guard ring of the avalanche diode through the connecting unit to relieve the edge breakdown.

摘要翻译： 本发明公开了一种具有保护环结构的雪崩光电二极管及其制造方法，所述雪崩光电二极管通过外部电压消除边缘击穿，所述外部电压通过附着于保护环的金属焊盘而施加。 具有保护环结构的雪崩光电二极管包括层叠在基板上的多个半导体层; 部分地形成在半导体层之上的有源区; 保护环，其形成在半导体层上方并且被设置成与有源区间隔开并且具有包围有源区的环形形状; 以及连接单元，其形成在所述半导体层上以与所述保护环电连接，以将外部电压施加到所述保护环区域。 因此，通过连接单元将外部电压施加到雪崩二极管的保护环，以缓解边缘故障。

公开(公告)号：US20140363937A1

公开(公告)日：2014-12-11

申请号：US14308000

申请日：2014-06-18

申请人： Electronics and Telecommunications Research Institute

发明人： Woo Jin CHANG ,  Jong-Won LIM ,  Ho Kyun AHN ,  Sang Choon KO ,  Sung Bum BAE ,  Chull Won JU ,  Young Rak PARK ,  Jae Kyoung MUN ,  Eun Soo NAM

IPC分类号： H01L29/66 ,  H01L29/40

CPC分类号： H01L29/66901 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

摘要： Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.

摘要翻译： 公开了功率半导体器件及其制造方法，其可以通过形成在栅电极和漏电极之间的场板来增加器件的击穿电压，并且同时实现更容易的制造工艺。 根据本公开的示例性实施例的功率半导体器件包括形成在衬底上的源电极和漏电极; 形成在所述源电极和所述漏电极之间的电介质层具有比所述两个电极的高度低的高度，并且包括暴露所述衬底的蚀刻部分; 形成在蚀刻部分上的栅电极; 形成在栅电极和漏电极之间的电介质层上的场板; 以及配置成连接场板和源电极的金属。

公开(公告)号：US20140103539A1

公开(公告)日：2014-04-17

申请号：US14021269

申请日：2013-09-09

申请人： Electronics and Telecommunications Research Institute

发明人： Byoung-Gue MIN ,  Sang Choon KO ,  Jong-Won Lim ,  Hokyun AHN ,  Hyung Sup YOON ,  Jae Kyoung MUN ,  Eun Soo NAM

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L21/28 ,  H01L21/02

CPC分类号： H01L23/535 ,  H01L21/02365 ,  H01L21/28 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

摘要翻译： 半导体器件可以包括具有下通孔的衬底，具有暴露衬底的顶表面的开口的外延层，设置在衬底的顶表面上并包括第一，第二和第三电极的半导体芯片， 连接到第一电极的上金属层，设置在上金属层上并具有上通孔的支撑基板，设置在基板上并延伸到上通孔中的上焊盘，连接到第二电极的下焊盘 以及覆盖基板的底面的下金属层，并且通过下通路孔与下焊盘连接。