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公开(公告)号：US20150380354A1
公开(公告)日：2015-12-31
申请号：US14845435
申请日：2015-09-04
Inventor： Byoung-Gue MIN , Sang Choon KO , Jong-Won LIM , Hokyun AHN , Hyung Sup YOON , Jae Kyoung MUN , Eun Soo NAM
IPC: H01L23/535 , H01L23/48
CPC classification number: H01L23/535 , H01L21/02365 , H01L21/28 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.
Abstract translation: 半导体器件可以包括具有下通孔的衬底，具有暴露衬底的顶表面的开口的外延层，设置在衬底的顶表面上并包括第一，第二和第三电极的半导体芯片， 连接到第一电极的上金属层，设置在上金属层上并具有上通孔的支撑基板，设置在基板上并延伸到上通孔中的上焊盘，连接到第二电极的下焊盘 以及覆盖基板的底面的下金属层，并且通过下通路孔与下焊盘连接。
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公开(公告)号：US20140363937A1
公开(公告)日：2014-12-11
申请号：US14308000
申请日：2014-06-18
Inventor： Woo Jin CHANG , Jong-Won LIM , Ho Kyun AHN , Sang Choon KO , Sung Bum BAE , Chull Won JU , Young Rak PARK , Jae Kyoung MUN , Eun Soo NAM
CPC classification number: H01L29/66901 , H01L29/2003 , H01L29/401 , H01L29/402 , H01L29/42316 , H01L29/66462 , H01L29/7786
Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.
Abstract translation: 公开了功率半导体器件及其制造方法，其可以通过形成在栅电极和漏电极之间的场板来增加器件的击穿电压，并且同时实现更容易的制造工艺。 根据本公开的示例性实施例的功率半导体器件包括形成在衬底上的源电极和漏电极; 形成在所述源电极和所述漏电极之间的电介质层具有比所述两个电极的高度低的高度，并且包括暴露所述衬底的蚀刻部分; 形成在蚀刻部分上的栅电极; 形成在栅电极和漏电极之间的电介质层上的场板; 以及配置成连接场板和源电极的金属。
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公开(公告)号：US20140103539A1
公开(公告)日：2014-04-17
申请号：US14021269
申请日：2013-09-09
Inventor： Byoung-Gue MIN , Sang Choon KO , Jong-Won Lim , Hokyun AHN , Hyung Sup YOON , Jae Kyoung MUN , Eun Soo NAM
IPC: H01L21/768 , H01L23/48 , H01L21/28 , H01L21/02
CPC classification number: H01L23/535 , H01L21/02365 , H01L21/28 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.
Abstract translation: 半导体器件可以包括具有下通孔的衬底，具有暴露衬底的顶表面的开口的外延层，设置在衬底的顶表面上并包括第一，第二和第三电极的半导体芯片， 连接到第一电极的上金属层，设置在上金属层上并具有上通孔的支撑基板，设置在基板上并延伸到上通孔中的上焊盘，连接到第二电极的下焊盘 以及覆盖基板的底面的下金属层，并且通过下通路孔与下焊盘连接。
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公开(公告)号：US20220223696A1
公开(公告)日：2022-07-14
申请号：US17574271
申请日：2022-01-12
Inventor： Jae Kyoung MUN , Woojin CHANG , Yoo Jin JANG , Kyu Jun CHO
Abstract: Disclosed is a method for manufacturing a power semiconductor device. The method includes forming a lower active layer on a substrate, forming an upper active layer on both sides of the lower active layer, forming a source electrode, a drain electrode, and a gate electrode on the upper active layer and the lower active layer, and forming a heat dissipating and electrical ground electrode penetrating the substrate and the lower active layer and connected to a lower surface of the lower active layer. The upper active layer may be epitaxially grown at a high doping concentration by a selective deposition method using a mask layer that exposes a portion of the lower active layer as a blocking layer.
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公开(公告)号：US20150129890A1
公开(公告)日：2015-05-14
申请号：US14583858
申请日：2014-12-29
Inventor： Hokyun AHN , Jong-Won LIM , Jeong-Jin KIM , Hae Cheon KIM , Jae Kyoung MUN , Eun Soo NAM
IPC: H01L29/778 , H01L29/51 , H01L29/205 , H01L29/20 , H01L29/201
CPC classification number: H01L29/7787 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/42316 , H01L29/4236 , H01L29/42376 , H01L29/51 , H01L29/518 , H01L29/66462 , H01L29/7786
Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.
Abstract translation: 场效应晶体管包括依次层叠在基板上的有源层和覆盖层，以及贯穿封盖层并与活性层相邻的栅电极。 栅电极包括与有源层相邻的脚部和具有大于脚部的宽度的宽度的头部。 栅电极的端部的脚部的宽度小于栅电极的另一部分的头部的宽度，并且大于栅极的另一部分的脚部的宽度。 栅电极的端部的脚部进一步穿过有源层，以与衬底相邻。
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Patent Agency Ranking
公开(公告)号：US20140097685A1
公开(公告)日：2014-04-10
申请号：US14040102
申请日：2013-09-27
Inventor： Yong il JUN , SANG CHOON KO , Jae Kyoung MUN , Dae Woo LEE , Kyu-Seok LEE , Ho Young KIM , Chul Won JU
CPC classification number: H02J1/04 , H02H3/20 , H02H7/10 , H02M2001/0074 , H02M2001/0087 , Y10T307/406
Abstract: The inventive concept relates to a system supplying a constant current direct current power to serial loads connected in series with one another.The inventive concept is constituted by a constant current source power supply unit outputting a predetermined direct current, a load connection unit having the same rated current characteristic as the constant current source, a load connection unit having a rated current characteristic smaller than the constant current source, a load connection unit having a rated current characteristic greater than the constant current source, a load connection unit having a rated current characteristic greater or smaller than the constant current source and a circuit controlling or protecting them.
Abstract translation: 本发明的概念涉及向彼此串联连接的串联负载提供恒定电流直流电力的系统。 本发明的概念由输出预定直流电流的恒流源电源单元，与恒流源具有相同额定电流特性的负载连接单元构成，具有小于恒定电流源的额定电流特性的负载连接单元 具有大于恒流源的额定电流特性的负载连接单元，具有大于或小于恒流源的额定电流特性的负载连接单元和控制或保护恒流源的电路。
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公开(公告)号：US20160380119A1
公开(公告)日：2016-12-29
申请号：US15084874
申请日：2016-03-30
Inventor： Dong Yun JUNG , Hyun Soo LEE , Sang Choon KO , Jeong-Jin KIM , Zin-Sig KIM , Jeho NA , Eun Soo NAM , Jae Kyoung MUN , Young Rak PARK , Sung-Bum BAE , Hyung Seok LEE , Woojin CHANG , Hyungyu JANG , Chi Hoon JUN
IPC: H01L29/872 , H01L29/205 , H01L29/45 , H01L21/02 , H01L23/29 , H01L29/47 , H01L29/66 , H01L21/306 , H01L29/20 , H01L23/31
CPC classification number: H01L21/0228 , H01L23/291 , H01L23/3178 , H01L29/2003 , H01L29/205 , H01L29/66212 , H01L29/872
Abstract: A first nitride semiconductor layer of a semiconductor device is provided on a substrate, a second nitride semiconductor layer is provided on the first nitride semiconductor layer, a first ohmic metal and a second ohmic metal are provided on the second nitride semiconductor layer, a recess region is provided in the second nitride semiconductor layer between the first ohmic metal and the second ohmic metal, a passivation layer covers side of the first ohmic metal and a bottom surface and sides of the recess region, and a Schottky electrode is provided on the first ohmic metal and extends into the recess region.
Abstract translation: 半导体器件的第一氮化物半导体层设置在衬底上，第二氮化物半导体层设置在第一氮化物半导体层上，第一欧姆金属和第二欧姆金属设置在第二氮化物半导体层上，凹部 在所述第一欧姆金属和所述第二欧姆金属之间的所述第二氮化物半导体层中设置钝化层，所述钝化层覆盖所述第一欧姆金属的一侧，并且所述钝化层覆盖所述凹部区域的底表面和所述侧面，并且所述第一欧姆金属的肖特基电极 金属并延伸到凹陷区域中。
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8.发明申请IMPEDANCE MATCHING CIRCUIT, POWER AMPLIFIER AND MANUFACTURING METHOD FOR VARIABLE CAPACITOR 审中-公开阻抗匹配电路，功率放大器和可变电容器的制造方法公开(公告)号：US20160020147A1
公开(公告)日：2016-01-21
申请号：US14862123
申请日：2015-09-22
Inventor： Jongmin LEE , Byoung-Gue MIN , Seong-il KIM , Hyung Sup YOON , Jae Kyoung MUN , Eun Soo NAM
IPC: H01L21/8222 , H01L27/06
CPC classification number: H01L21/8222 , H01G7/00 , H01L27/0647 , H01L27/0658 , H01L29/93 , H03F1/565 , H03F3/21 , H03F2200/36 , H03F2200/378 , H03F2200/387 , H03F2200/391 , H03H7/38 , Y10T29/43
Abstract: A manufacturing method for a variable capacitor includes forming a first element of which a capacitance value depends on a voltage applied to both of two terminals of a first area on a substrate, forming a second element having a capacitance value fixed to a second area on the substrate adjacent to the first area, and forming metallic wires for connecting the first element and the second element and connecting the first element and the second element with the outside. The first element maybe a bipolar transistor that may include a diode. The second element maybe a capacitor that includes a dielectric.
Abstract translation: 一种可变电容器的制造方法，包括：形成电容值取决于施加到基板上的第一区域的两端的电压的第一元件，形成具有固定在第二区域上的电容值的第二元件 基板，与第一区域相邻，并且形成用于连接第一元件和第二元件的金属线，并且将第一元件和第二元件与外部连接。 第一个元件可以是可以包括二极管的双极晶体管。 第二元件可以是包括电介质的电容器。
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公开(公告)号：US20150171188A1
公开(公告)日：2015-06-18
申请号：US14633984
申请日：2015-02-27
Inventor： Hyung Sup YOON , Byoung-Gue MIN , Jong-Won LIM , Hokyun AHN , Seong-Il Kim , Sang Heung LEE , Dong Min KANG , Chull Won JU , Jae Kyoung MUN
IPC: H01L29/66 , H01L29/201 , H01L21/02 , H01L21/28 , H01L21/311 , H01L29/423 , H01L29/20 , H01L29/205
CPC classification number: H01L29/66462 , H01L21/02118 , H01L21/0217 , H01L21/02178 , H01L21/0254 , H01L21/28264 , H01L21/28593 , H01L21/31111 , H01L21/31144 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/404 , H01L29/42316 , H01L29/42376 , H01L29/778 , H01L29/7786
Abstract: A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.
Abstract translation: 提供场效应晶体管。 场效应晶体管可以包括衬底上的覆盖层，覆盖层上的源欧姆电极和漏极欧姆电极，堆叠在覆盖层上以覆盖源极和漏极欧姆电极的第一绝缘层和第二绝缘层， 包括脚部和头部的栅格电极，所述脚部分连接到所述源欧姆电极和所述漏极欧姆电极之间的衬底，并且所述头部从所述腿部延伸以覆盖所述源极欧姆电极和所述漏极欧姆电极的顶表面 所述第二绝缘层，在所述第二绝缘层上覆盖所述栅格电极的第一平坦化层和所述第一平坦化层上的第一电极，所述第一电极连接到所述源欧姆电极或所述漏极欧姆电极。
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公开(公告)号：US20170201247A1
公开(公告)日：2017-07-13
申请号：US15217271
申请日：2016-07-22
Inventor： Woojin CHANG , Sang Choon KO , Jae Kyoung MUN , Young Rak PARK
IPC: H03K17/081 , H03K17/74
CPC classification number: H03K17/08104 , H03K17/0822 , H03K17/74
Abstract: A cascode switch circuit includes a first transistor, a second transistor, and a protector. A first transistor receives a signal from a first terminal through a first end and transfers the signal to a second end in response to a first control signal. A second transistor delivers the signal that the first transistor transfers to a second terminal in response to a second control signal. A protector is connected between a gate of the first transistor and the second terminal. The first control signal is provided to allow the first transistor to operate in a normally-on state. The second control signal is provided to allow the second transistor to operate in a normally-off state.
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