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公开(公告)号：US20210083632A1
公开(公告)日：2021-03-18
申请号：US16941691
申请日：2020-07-29
Inventor： Woojin CHANG , SEONG-IL KIM , Sang-Heung LEE , Jongmin LEE
Abstract: Provided is an amplification circuit for amplifying an input signal. The amplification circuit includes an input stage including an input matching circuit that receives the input signal and an input attenuation circuit that attenuates a gain for the input signal outside an operating frequency band of the amplification circuit, a transistor that amplifies the input signal provided from the input stage, and an output stage including an output matching circuit that receives a signal amplified by the transistor and an output attenuation circuit that attenuates the gain for the input signal outside the operating frequency band of the amplification circuit, and the input attenuation circuit includes a first resistor and a second resistor that are connected to a ground voltage, a first passive element connected between the input matching circuit and the second resistor, and a second passive element connected between the first passive element and the first resistor.
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公开(公告)号：US20160380119A1
公开(公告)日：2016-12-29
申请号：US15084874
申请日：2016-03-30
Inventor： Dong Yun JUNG , Hyun Soo LEE , Sang Choon KO , Jeong-Jin KIM , Zin-Sig KIM , Jeho NA , Eun Soo NAM , Jae Kyoung MUN , Young Rak PARK , Sung-Bum BAE , Hyung Seok LEE , Woojin CHANG , Hyungyu JANG , Chi Hoon JUN
IPC: H01L29/872 , H01L29/205 , H01L29/45 , H01L21/02 , H01L23/29 , H01L29/47 , H01L29/66 , H01L21/306 , H01L29/20 , H01L23/31
CPC classification number: H01L21/0228 , H01L23/291 , H01L23/3178 , H01L29/2003 , H01L29/205 , H01L29/66212 , H01L29/872
Abstract: A first nitride semiconductor layer of a semiconductor device is provided on a substrate, a second nitride semiconductor layer is provided on the first nitride semiconductor layer, a first ohmic metal and a second ohmic metal are provided on the second nitride semiconductor layer, a recess region is provided in the second nitride semiconductor layer between the first ohmic metal and the second ohmic metal, a passivation layer covers side of the first ohmic metal and a bottom surface and sides of the recess region, and a Schottky electrode is provided on the first ohmic metal and extends into the recess region.
Abstract translation: 半导体器件的第一氮化物半导体层设置在衬底上，第二氮化物半导体层设置在第一氮化物半导体层上，第一欧姆金属和第二欧姆金属设置在第二氮化物半导体层上，凹部 在所述第一欧姆金属和所述第二欧姆金属之间的所述第二氮化物半导体层中设置钝化层，所述钝化层覆盖所述第一欧姆金属的一侧，并且所述钝化层覆盖所述凹部区域的底表面和所述侧面，并且所述第一欧姆金属的肖特基电极 金属并延伸到凹陷区域中。
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公开(公告)号：US20160225631A1
公开(公告)日：2016-08-04
申请号：US15093814
申请日：2016-04-08
Inventor： Chi Hoon JUN , Sang Choon KO , Seok-Hwan MOON , Woojin CHANG , Sung-Bum BAE , Young Rak PARK , Je Ho NA , Jae Kyoung MUN , Eun Soo NAM
IPC: H01L21/3065 , H01L21/308 , H01L21/3205 , H01L23/367
CPC classification number: H01L21/3065 , H01L21/3081 , H01L21/32051 , H01L23/367 , H01L23/467 , H01L23/473 , H01L2924/0002 , H01L2924/00
Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.
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公开(公告)号：US20150187886A1
公开(公告)日：2015-07-02
申请号：US14311675
申请日：2014-06-23
Inventor： Young Rak PARK , Sang Choon KO , Woojin CHANG , Jae Kyoung MUN , Sung-Bum BAE
IPC: H01L29/20 , H01L29/49 , H01L29/417 , H01L29/205
CPC classification number: H01L29/66462 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/4236 , H01L29/66431 , H01L29/737 , H01L29/778 , H01L29/7786
Abstract: Provided is a nitride semiconductor device including: a substrate having through via holes; first and second nitride semiconductor layers sequentially stacked on the substrate; drain electrodes and source electrodes provided on the second nitride semiconductor layer; and an insulating pattern provided on the second nitride semiconductor layer, the insulating pattern having upper via holes provided on the drain electrodes, wherein the through via holes are extended into the first and second nitride semiconductor layers and expose a bottom of each of the source electrodes.
Abstract translation: 提供一种氮化物半导体器件，包括：具有通孔的衬底; 顺序堆叠在基板上的第一和第二氮化物半导体层; 设置在第二氮化物半导体层上的漏电极和源电极; 以及设置在所述第二氮化物半导体层上的绝缘图案，所述绝缘图案具有设置在所述漏电极上的上通孔，所述贯通通孔延伸到所述第一氮化物半导体层和所述第二氮化物半导体层中，并暴露出每个所述源电极的底部 。
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公开(公告)号：US20150187599A1
公开(公告)日：2015-07-02
申请号：US14310784
申请日：2014-06-20
Inventor： Sang Choon KO , Jae Kyoung MUN , Woojin CHANG , Sung-Bum BAE , Young Rak PARK , Chi Hoon JUN , Seok-Hwan MOON , Woo-Young JANG , Jeong-Jin KIM , Hyungyu JANG , Je Ho NA , Eun Soo NAM
IPC: H01L21/321 , H01L21/283 , H01L21/02
CPC classification number: H01L21/3212 , H01L21/0254 , H01L21/283 , H01L21/28575 , H01L21/28581 , H01L29/2003 , H01L29/41766 , H01L29/452 , H01L29/66462 , H01L29/7786
Abstract: Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.
Abstract translation: 提供一种制造氮化物半导体器件的方法。 该方法包括在生长衬底上形成多个电极，在其上依次层叠有第一和第二氮化物半导体层，分别在多个电极上形成上部金属层，去除生长衬底以暴露第一氮化物半导体层的下表面 并且在第一氮化物半导体层的暴露的下表面上顺序地形成第三氮化物半导体层和下金属层。
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Patent Agency Ranking
公开(公告)号：US20220223696A1
公开(公告)日：2022-07-14
申请号：US17574271
申请日：2022-01-12
Inventor： Jae Kyoung MUN , Woojin CHANG , Yoo Jin JANG , Kyu Jun CHO
Abstract: Disclosed is a method for manufacturing a power semiconductor device. The method includes forming a lower active layer on a substrate, forming an upper active layer on both sides of the lower active layer, forming a source electrode, a drain electrode, and a gate electrode on the upper active layer and the lower active layer, and forming a heat dissipating and electrical ground electrode penetrating the substrate and the lower active layer and connected to a lower surface of the lower active layer. The upper active layer may be epitaxially grown at a high doping concentration by a selective deposition method using a mask layer that exposes a portion of the lower active layer as a blocking layer.
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公开(公告)号：US20170213904A1
公开(公告)日：2017-07-27
申请号：US15414156
申请日：2017-01-24
Inventor： Jeho NA , Hyung Seok LEE , Chi Hoon JUN , Sang Choon KO , Myungjoon KWACK , Young Rak PARK , Woojin CHANG , Hyun-Gyu JANG , Dong Yun JUNG
IPC: H01L29/778 , H01L29/205 , H01L29/66 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/20 , H01L23/31
CPC classification number: H01L29/7787 , H01L23/315 , H01L23/3171 , H01L29/0649 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/41758 , H01L29/42364 , H01L29/42372 , H01L29/66462 , H01L29/7786
Abstract: A semiconductor device includes a semiconductor structure including a substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer, a first passivation pattern provided on the semiconductor structure, and first and second conductive patterns provided on the semiconductor structure and spaced from the first passivation pattern.
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公开(公告)号：US20160247792A1
公开(公告)日：2016-08-25
申请号：US14815378
申请日：2015-07-31
Inventor： Woojin CHANG
IPC: H01L25/18 , H01L23/00 , H01L23/492 , H01L23/48 , H01L25/07
CPC classification number: H01L25/18 , H01L23/492 , H01L23/49562 , H01L23/49575 , H01L23/49844 , H01L24/48 , H01L24/49 , H01L25/072 , H01L2224/48137 , H01L2224/48177 , H01L2924/00014 , H01L2924/1033 , H01L2924/13091 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: Provided is switch circuit including first and second transistors, a source pad connected to a second node of the second transistor through a first signal path and connected to a gate node of the first transistor through a second signal path, a gate pad connected to a gate node of the second transistor through a third signal path; and a drain pad connected to a first node of the first transistor through a fourth signal path, wherein a second node of the first transistor and a first node of the second transistor are connected to each other through a fifth signal path, and the gate node of the first transistor and the second node of the second transistor are connected to each other through a sixth signal path separated from the first and second signal paths.
Abstract translation: 提供了包括第一和第二晶体管的开关电路，源极焊盘通过第一信号路径连接到第二晶体管的第二节点，并通过第二信号路径连接到第一晶体管的栅极节点，连接到栅极的栅极焊盘 通过第三信号路径的第二晶体管的节点; 以及通过第四信号路径连接到第一晶体管的第一节点的漏极焊盘，其中第一晶体管的第二节点和第二晶体管的第一节点通过第五信号路径彼此连接，并且栅极节点 的第一晶体管和第二晶体管的第二节点通过与第一和第二信号路径分离的第六信号路径彼此连接。
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公开(公告)号：US20230142553A1
公开(公告)日：2023-05-11
申请号：US17886061
申请日：2022-08-11
Inventor： Woojin CHANG , Dong Min KANG , BYOUNG-GUE MIN , JONG YUL PARK , JONGMIN LEE , YOO JIN JANG , KYU JUN CHO , Hong Gu JI
Abstract: Disclosed is a frequency mixer. The frequency mixer includes a first matching circuit that generates a matched local oscillator (LO) signal based on an LO signal, a non-linear circuit that generates a non-linear LO signal based on the matched LO signal, a second matching circuit that generates a matched radio frequency (RF) signal based on an RF signal, a mixing circuit that generates a mixed signal based on a mixing of the non-linear LO signal and the matched RF signal, a third matching circuit that generates an intermediate frequency (IF) signal based on the mixed signal, wherein the non-linear circuit includes a non-linear transistor, a bias transistor, and an internal matching circuit connected in series.
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公开(公告)号：US20180145684A1
公开(公告)日：2018-05-24
申请号：US15654792
申请日：2017-07-20
Inventor： Woojin CHANG , Jong-Won LIM , Dong Min KANG , Dong-Young KIM , Seong-il KIM , Hae Cheon KIM , Jae Won DO , BYOUNG-GUE MIN , Min Jeong SHIN , Hokyun AHN , Hyung Sup YOON , Sang-Heung LEE , JONGMIN LEE , Sungjae CHANG , Yoo Jin JANG , HYUNWOOK JUNG , Kyu Jun CHO , Hong Gu JI
IPC: H03K17/687 , H03K17/693 , G11C5/14 , H03K19/0175 , H03K3/353
CPC classification number: H03K17/687 , G11C5/14 , H03K3/353 , H03K17/08122 , H03K17/102 , H03K17/122 , H03K17/145 , H03K17/162 , H03K17/28 , H03K17/693 , H03K19/0175
Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.
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