公开(公告)号：US20180145684A1

公开(公告)日：2018-05-24

申请号：US15654792

申请日：2017-07-20

Applicant: Electronics and Telecommunications Research Institute

Inventor： Woojin CHANG ,  Jong-Won LIM ,  Dong Min KANG ,  Dong-Young KIM ,  Seong-il KIM ,  Hae Cheon KIM ,  Jae Won DO ,  BYOUNG-GUE MIN ,  Min Jeong SHIN ,  Hokyun AHN ,  Hyung Sup YOON ,  Sang-Heung LEE ,  JONGMIN LEE ,  Sungjae CHANG ,  Yoo Jin JANG ,  HYUNWOOK JUNG ,  Kyu Jun CHO ,  Hong Gu JI

IPC: H03K17/687 ,  H03K17/693 ,  G11C5/14 ,  H03K19/0175 ,  H03K3/353

CPC classification number: H03K17/687 ,  G11C5/14 ,  H03K3/353 ,  H03K17/08122 ,  H03K17/102 ,  H03K17/122 ,  H03K17/145 ,  H03K17/162 ,  H03K17/28 ,  H03K17/693 ,  H03K19/0175

Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.