公开(公告)号：US20230115787A1

公开(公告)日：2023-04-13

申请号：US17879047

申请日：2022-08-02

申请人： Electronics and Telecommunications Research Institute

发明人： Hong Gu JI ,  Dong Min KANG ,  BYOUNG-GUE MIN ,  JONGMIN LEE ,  Kyu Jun CHO

IPC分类号： H03K17/687

摘要： Disclosed is a switch circuit for an ultra-high frequency band, which includes a transistor including a first terminal connected to an input stage, a second terminal connected to an output stage, and a gate terminal, an inductor connected to the transistor in parallel, between the input stage and the output stage, a variable gate driver to apply a gate input voltage to the gate terminal and, an input resistor connected between the variable gate driver and the gate terminal. The variable gate driver adjusts the gate input voltage to be in one of a first voltage level for turning on the transistor and a second voltage level for turning off the transistor. The second voltage level varies depending on a capacitance between the first terminal and the second terminal, when the transistor is in a turn-off state.

公开(公告)号：US20230142553A1

公开(公告)日：2023-05-11

申请号：US17886061

申请日：2022-08-11

申请人： Electronics and Telecommunications Research Institute

发明人： Woojin CHANG ,  Dong Min KANG ,  BYOUNG-GUE MIN ,  JONG YUL PARK ,  JONGMIN LEE ,  YOO JIN JANG ,  KYU JUN CHO ,  Hong Gu JI

IPC分类号： H03D7/12 ,  H03H7/38

CPC分类号： H03D7/125 ,  H03H7/38

摘要： Disclosed is a frequency mixer. The frequency mixer includes a first matching circuit that generates a matched local oscillator (LO) signal based on an LO signal, a non-linear circuit that generates a non-linear LO signal based on the matched LO signal, a second matching circuit that generates a matched radio frequency (RF) signal based on an RF signal, a mixing circuit that generates a mixed signal based on a mixing of the non-linear LO signal and the matched RF signal, a third matching circuit that generates an intermediate frequency (IF) signal based on the mixed signal, wherein the non-linear circuit includes a non-linear transistor, a bias transistor, and an internal matching circuit connected in series.

公开(公告)号：US20180145684A1

公开(公告)日：2018-05-24

申请号：US15654792

申请日：2017-07-20

申请人： Electronics and Telecommunications Research Institute

发明人： Woojin CHANG ,  Jong-Won LIM ,  Dong Min KANG ,  Dong-Young KIM ,  Seong-il KIM ,  Hae Cheon KIM ,  Jae Won DO ,  BYOUNG-GUE MIN ,  Min Jeong SHIN ,  Hokyun AHN ,  Hyung Sup YOON ,  Sang-Heung LEE ,  JONGMIN LEE ,  Sungjae CHANG ,  Yoo Jin JANG ,  HYUNWOOK JUNG ,  Kyu Jun CHO ,  Hong Gu JI

IPC分类号： H03K17/687 ,  H03K17/693 ,  G11C5/14 ,  H03K19/0175 ,  H03K3/353

CPC分类号： H03K17/687 ,  G11C5/14 ,  H03K3/353 ,  H03K17/08122 ,  H03K17/102 ,  H03K17/122 ,  H03K17/145 ,  H03K17/162 ,  H03K17/28 ,  H03K17/693 ,  H03K19/0175

摘要： Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.