公开(公告)号：US11990910B2

公开(公告)日：2024-05-21

申请号：US17729844

申请日：2022-04-26

Applicant: Nordic Semiconductor ASA

Inventor： Harald Garvik

IPC: H03K3/00 ,  H03K3/353 ,  H03K5/01 ,  H03K5/02

CPC classification number: H03K3/353 ,  H03K5/01 ,  H03K5/023

Abstract: A circuit portion comprises a load circuit portion and a bias circuit portion. The load circuit portion comprises a load transistor. The bias circuit portion comprises a replica transistor matched to the load transistor and connected to the load transistor at a node such that when a current flows through the replica transistor, a current proportional to the current through the replica transistor flows through the load transistor. The bias circuit portion also comprises a current input for receiving an input current, a supply voltage input for receiving a supply voltage, and a feedback loop arranged to: adjust a voltage at the node connecting the replica transistor and the load transistor such that the replica transistor conducts a current proportional to the input current, and counteract variations in the voltage at the node connecting the replica transistor and the load transistor arising from changes in the supply voltage.

公开(公告)号：US11736095B2

公开(公告)日：2023-08-22

申请号：US17987189

申请日：2022-11-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel Ramirez ,  Sudipto Chakraborty

IPC: H03K3/00 ,  H03K3/353 ,  H03K5/13 ,  H03K5/00

CPC classification number: H03K3/353 ,  H03K5/13 ,  H03K2005/00195

Abstract: A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.

公开(公告)号：US20180123572A1

公开(公告)日：2018-05-03

申请号：US15612694

申请日：2017-06-02

Applicant: SK hynix Inc.

Inventor： Jeong-Eun SONG

IPC: H03K5/12 ,  H03K3/353

CPC classification number: H03K5/12 ,  H03K3/353 ,  H03K4/90 ,  H03K6/04

Abstract: Provided is an electronic device including a ramp signal generation circuit configured to generate a ramp signal having a second slope that is greater by a first level than a first slope which corresponds to an analog gain, and a slope correction circuit configured to correct the second slope of the ramp signal by the first level to obtain the first slope.

公开(公告)号：US09608606B2

公开(公告)日：2017-03-28

申请号：US14955613

申请日：2015-12-01

Applicant: AMAZING MICROELECTRONIC CORP.

Inventor： Long-Xi Chang ,  Ryan Hsin-Chin Jiang

IPC: H03K5/01 ,  H03K3/353

CPC classification number: H03K5/01 ,  H03K3/353 ,  H03K19/00361

Abstract: A slope control circuit is connected between a replica circuit and a controller area network bus. The replica circuit generates an upper and a lower feedback signal. The slope control circuit receives and is driven by the feedback signals for controlling a voltage slope of a high-level output and a low-level output. The slope control circuit comprises an upper and a lower driving circuit, individually connected between the replica circuit, the high-level output and the low-level output. The upper driving circuit and the lower driving circuit respectively include at least one charging and discharging circuit. By controlling the charging and discharging circuit, the present invention controls decreasing voltage slope of the high-level output to be symmetric to increasing voltage slope of the low-level output, and delay time of the circuit switching between different operating modes to be equivalent.

公开(公告)号：US09438209B2

公开(公告)日：2016-09-06

申请号：US14583963

申请日：2014-12-29

Applicant: International Business Machines Corporation

Inventor： Andrew D. Davies ,  Grant P. Kesselring ,  Christopher W. Steffen ,  James D. Strom

IPC: H03K5/04 ,  H03K3/017 ,  H03L7/10

CPC classification number: H03K3/017 ,  H03K3/353 ,  H03K3/356104 ,  H03K5/1252 ,  H03L7/10

Abstract: A method and a clock receiver circuit for implementing low jitter and enhanced duty cycle, and a design structure on which the subject circuit resides are provided. The clock receiver circuit accepts single-ended complementary metal oxide semiconductor (CMOS) and differential clock signals. The clock receiver circuit includes input circuitry coupled to a differential pair that biasing a reference clock and allows for single-ended or differential clock signals. The differential pair uses multiple current mirrors for switching the polarity of the input signals to achieve enhanced jitter performance, and cross coupled inverters for retaining signal symmetry.

Abstract translation: 一种用于实现低抖动和增强占空比的方法和时钟接收器电路，以及设置有被摄体电路的设计结构。 时钟接收器电路接受单端互补金属氧化物半导体（CMOS）和差分时钟信号。 时钟接收器电路包括耦合到差分对的输入电路，其偏置参考时钟并允许单端或差分时钟信号。 差分对使用多个电流镜来切换输入信号的极性以实现增强的抖动性能，以及用于保持信号对称性的交叉耦合反相器。

公开(公告)号：US20160182035A1

公开(公告)日：2016-06-23

申请号：US15056846

申请日：2016-02-29

Applicant: Renesas Electronics Corporation

Inventor： Sakae Nakajima

IPC: H03K17/567 ,  H01L27/088 ,  H01L29/78 ,  G01R31/44 ,  H03K17/687 ,  H05B37/02 ,  H05B37/03 ,  G01R19/00 ,  H01L27/02 ,  H01L29/739

CPC classification number: H03K17/567 ,  G01R19/0084 ,  G01R31/44 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/7395 ,  H01L29/7815 ,  H01L29/7825 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06134 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49107 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/13055 ,  H03K3/353 ,  H03K17/687 ,  H05B37/0227 ,  H05B37/03 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2924/00012

Abstract: A driver IC (Integrated Circuit) includes a power supply terminal; an output terminal to be coupled to a load element; a connection node on a current path between the power supply terminal and the output terminal; a substrate resistance, having one end coupled to the connection node; an output transistor including a gate, wherein the output transistor is coupled in series with the substrate resistance through the connection node; a resistance, having one end coupled to an other end of the substrate resistance; and a voltage detecting circuit configured to detect a voltage depending on a voltage between the one end of the substrate resistance and the other end of the substrate resistance, and to output an output signal, which is as an output of the voltage detecting circuit, to the gate of the output transistor.

Abstract translation: 驱动器IC（集成电路）包括电源端子; 要耦合到负载元件的输出端子; 电源端子和输出端子之间的电流路径上的连接节点; 衬底电阻，其一端耦合到所述连接节点; 包括栅极的输出晶体管，其中所述输出晶体管通过所述连接节点与所述衬底电阻串联耦合; 电阻，其一端耦合到衬底电阻的另一端; 以及电压检测电路，被配置为根据基板电阻的一端和基板电阻的另一端之间的电压来检测电压，并将作为电压检测电路的输出的输出信号输出到 输出晶体管的栅极。

公开(公告)号：US20150333742A1

公开(公告)日：2015-11-19

申请号：US14808503

申请日：2015-07-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Sakae Nakajima

IPC: H03K3/353 ,  H01L27/088 ,  H01L27/02

CPC classification number: H03K17/567 ,  G01R19/0084 ,  G01R31/44 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/7395 ,  H01L29/7815 ,  H01L29/7825 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06134 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49107 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/13055 ,  H03K3/353 ,  H03K17/687 ,  H05B37/0227 ,  H05B37/03 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2924/00012

Abstract: A semiconductor high-side driver including; an input terminal; an output terminal to be coupled to a load element; an output MOS transistor having a drain coupled to a power supply terminal, a source coupled to the output terminal and a gate; a sense MOS transistor having a drain coupled to the power supply terminal, a gate coupled to the gate of the output MOS transistor and a source; a control circuit coupled to the input terminal and provides a control signal to the gate of the output MOS transistor; and a voltage detection circuit which includes: a threshold voltage generation circuit having a first terminal coupled to the power supply terminal and a second terminal which generates a voltage lower than a voltage of the power supply terminal by a threshold voltage; and a comparator.

Abstract translation: 一种半导体高侧驱动器，包括： 一个输入端; 要耦合到负载元件的输出端子; 输出MOS晶体管，其具有耦合到电源端子的漏极，耦合到输出端子的栅极和栅极; 感测MOS晶体管，其具有耦合到所述电源端子的漏极，耦合到所述输出MOS晶体管的栅极的栅极和源极; 控制电路，耦合到所述输入端，并向所述输出MOS晶体管的栅极提供控制信号; 以及电压检测电路，其包括：阈值电压产生电路，具有耦合到所述电源端子的第一端子和产生低于所述电源端子的电压的电压阈值电压的第二端子; 和比较器。

公开(公告)号：US09153688B2

公开(公告)日：2015-10-06

申请号：US14307674

申请日：2014-06-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Sakae Nakajima

IPC: H01L29/78 ,  G01R19/00

CPC classification number: H03K17/567 ,  G01R19/0084 ,  G01R31/44 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/7395 ,  H01L29/7815 ,  H01L29/7825 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06134 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49107 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/13055 ,  H03K3/353 ,  H03K17/687 ,  H05B37/0227 ,  H05B37/03 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2924/00012

Abstract: A semiconductor device includes an N-type semiconductor region, a back electrode, first and second P-type base regions, first and second N+ diffusion layers, a gate insulating film, a gate electrode and a voltage detecting circuit. The first N+ diffusion layer functions as a source of an output MOS transistor and functions as a source of a sense MOS transistor. The gate electrode is provided to oppose the N-type semiconductor region and the first and second P-type base regions through the gate insulating film 40. A load current flows between the back electrode and the first N+ diffusion layer. The voltage detecting circuit generates a detection signal.

Abstract translation: 半导体器件包括N型半导体区域，背面电极，第一和第二P型基极区域，第一和第二N +扩散层，栅极绝缘膜，栅极电极和电压检测电路。 第一N +扩散层用作输出MOS晶体管的源极，并且用作读出MOS晶体管的源极。 栅电极通过栅极绝缘膜40与N型半导体区域和第一和第二P型基极区域相对。负载电流在背电极和第一N +扩散层之间流动。 电压检测电路产生检测信号。

公开(公告)号：US08779829B2

公开(公告)日：2014-07-15

申请号：US13781031

申请日：2013-02-28

Applicant: Panasonic Corporation

Inventor： Satoshi Yamaguchi ,  Tomohiro Hirayama

IPC: H03L5/00

CPC classification number: H03K3/353 ,  H03K3/356104

Abstract: The invention provides a level shift circuit which uses a low supply voltage level shift circuit as a first level shift element and a high supply voltage level shift circuit as a second level shift element and which is configured to switch these level shift circuits in accordance with supply voltage. The low supply voltage level shift circuit is in an operating state with its power supply turned ON when supply voltage is low and in a shut-down state with the power supply turned OFF to ensure the breakdown voltages of the elements when supply voltage is high. The high supply voltage level shift circuit is in a shut-down state with its power supply turned OFF when supply voltage is low and comes into an operating state with the power supply turned ON while ensuring the breakdown voltages of elements when supply voltage is high.

Abstract translation: 本发明提供了一种电平移位电路，其使用低电源电平移位电路作为第一电平移位元件和高电源电压电平移位电路作为第二电平移位元件，并且被配置为根据电源切换这些电平移位电路 电压。 当电源电压低时，低电源电平移位电路处于工作状态，其电源接通，并且在电源关闭时处于关断状态，以确保当电源电压高时元件的击穿电压。 当电源电压低时，高电源电平移位电路处于关断状态，当电源电压为低电平时，电源断开，并且在供电电压高时确保元件的击穿电压，电源接通，并进入运行状态。

公开(公告)号：US4339672A

公开(公告)日：1982-07-13

申请号：US56854

申请日：1979-07-12

Applicant: Katsuyuki Sato

Inventor： Katsuyuki Sato

IPC: G11C11/407 ,  H01L21/822 ,  H01L27/04 ,  H01L29/78 ,  H03H11/26 ,  H03K3/02 ,  H03K3/03 ,  H03K3/353 ,  H03K3/354 ,  H03K5/00 ,  H03K5/13 ,  H03K5/15 ,  H03K5/151 ,  H03L7/00 ,  H03K3/26 ,  H03K19/01

CPC classification number: H03K3/353 ,  H01L27/04 ,  H01L29/78 ,  H03H11/26 ,  H03K3/02 ,  H03K3/0315 ,  H03K3/354 ,  H03K5/13 ,  H03K5/133 ,  H03K5/15093 ,  H03L7/00 ,  H03K2005/00195

Abstract: A delay circuit includes first and second MISFETs and a capacitance element connected to the common juncture of the first and the second MISFETs. The electricity of the capacitance element is charged through the first MISFET and is discharged through the second MISFET. Since the first and the second MISFETs effectively perform a push-pull operation, a signal of a predetermined level and a predetermined delay time to be delivered to a circuit having a logic threshold voltage is derived from the common juncture.

Abstract translation: 延迟电路包括第一和第二MISFET以及连接到第一和第二MISFET的公共接点的电容元件。 电容元件的电荷通过第一MISFET充电，并通过第二MISFET放电。 由于第一MISFET和第二MISFET有效地执行推挽操作，因此从公共接点导出将要传送到具有逻辑阈值电压的电路的预定电平和预定延迟时间的信号。