-
公开(公告)号：US20160380119A1
公开(公告)日：2016-12-29
申请号：US15084874
申请日：2016-03-30
Inventor： Dong Yun JUNG , Hyun Soo LEE , Sang Choon KO , Jeong-Jin KIM , Zin-Sig KIM , Jeho NA , Eun Soo NAM , Jae Kyoung MUN , Young Rak PARK , Sung-Bum BAE , Hyung Seok LEE , Woojin CHANG , Hyungyu JANG , Chi Hoon JUN
IPC: H01L29/872 , H01L29/205 , H01L29/45 , H01L21/02 , H01L23/29 , H01L29/47 , H01L29/66 , H01L21/306 , H01L29/20 , H01L23/31
CPC classification number: H01L21/0228 , H01L23/291 , H01L23/3178 , H01L29/2003 , H01L29/205 , H01L29/66212 , H01L29/872
Abstract: A first nitride semiconductor layer of a semiconductor device is provided on a substrate, a second nitride semiconductor layer is provided on the first nitride semiconductor layer, a first ohmic metal and a second ohmic metal are provided on the second nitride semiconductor layer, a recess region is provided in the second nitride semiconductor layer between the first ohmic metal and the second ohmic metal, a passivation layer covers side of the first ohmic metal and a bottom surface and sides of the recess region, and a Schottky electrode is provided on the first ohmic metal and extends into the recess region.
Abstract translation: 半导体器件的第一氮化物半导体层设置在衬底上，第二氮化物半导体层设置在第一氮化物半导体层上，第一欧姆金属和第二欧姆金属设置在第二氮化物半导体层上，凹部 在所述第一欧姆金属和所述第二欧姆金属之间的所述第二氮化物半导体层中设置钝化层，所述钝化层覆盖所述第一欧姆金属的一侧，并且所述钝化层覆盖所述凹部区域的底表面和所述侧面，并且所述第一欧姆金属的肖特基电极 金属并延伸到凹陷区域中。
-
公开(公告)号：US20210335681A1
公开(公告)日：2021-10-28
申请号：US17217433
申请日：2021-03-30
Inventor： Hyun Gyu JANG , Dong Yun JUNG , Doo Hyung CHO , Kun Sik PARK , Jong Won LIM
IPC: H01L23/15 , H01L25/065 , H01L23/31 , H01L21/768 , H01L23/538 , H01L21/48
Abstract: A ceramic stacked semiconductor package and a method of packaging a ceramic stacked semiconductor is disclosed. Inner walls of junctions are formed between ceramic layers and a molding resin to have a non-uniform boundary shape (e.g., Z shape, an uneven shape, a zigzag shape, etc.) so that bonding areas and lengths of the molding resin and the ceramic layers are increased, and thus adhesion is improved and movement paths of moisture are increased, thereby improving anti-humidity property and reliability of the semiconductor package. Further, by arranging via-holes at different positions for each layer so as not to overlap each other between the layers, movement paths of moisture passing through the via-holes are increased, and thus the anti-humidity property and reliability of the stacked package are additionally improved.
-
公开(公告)号：US20170141704A1
公开(公告)日：2017-05-18
申请号：US15299519
申请日：2016-10-21
Inventor： Chi Hoon JUN , Sang Choon KO , Minki KIM , Jeho NA , Young Rak PARK , Junbo PARK , Hyun Soo LEE , Hyung Seok LEE , Hyun-Gyu JANG , Dong Yun JUNG
IPC: H02N2/18 , H01L41/113 , H01L29/872 , H01L29/84 , H01L29/20 , H01L29/205
CPC classification number: H02N2/186 , H01L27/20 , H01L29/2003 , H01L29/205 , H01L29/84 , H01L29/872 , H01L41/1136
Abstract: Provided is a hybrid diode device. The hybrid diode device includes a first lower nitride layer disposed on a substrate and including a first 2-dimensional electron gas (2DEG) layer, a second lower nitride layer extending from the first lower nitride layer to the outside of the substrate and including a second 2DEG layer, a first upper nitride layer disposed on the first lower nitride layer, a second upper nitride layer disposed on the second lower nitride layer, a first cap layer disposed on the first upper nitride layer, a second cap layer disposed on the second upper nitride layer, a first electrode structure connected to the first lower nitride layer and the first cap layer; and a second electrode structure connected to the second lower nitride layer and the first electrode structure. The second lower nitride layer generates electric energy through dynamic movement.
-
公开(公告)号：US20220020671A1
公开(公告)日：2022-01-20
申请号：US17380583
申请日：2021-07-20
Inventor： Dong Yun JUNG , Hyun Gyu JANG , Sung Kyu KWON , Kun Sik PARK , Jong Il WON , Seong Hyun LEE , Jong Won LIM , Doo Hyung CHO
IPC: H01L23/495 , H01L23/00
Abstract: The present invention minimizes parasitic inductance at the time of packaging a semiconductor that requires high efficiency and high-speed switching driving. In implementing a semiconductor package composed of one or more switching devices and one or more diode devices, the present invention provides a flip-stack structure in which a switching device is mounted on an insulating substrate or a metal frame, a flat metal is bonded onto the switching device, and a diode device is flipped and stacked on the flat metal, and accordingly, the flat metal with a large area is used for connection between the devices and between the devices and the insulating substrate, thereby minimizing parasitic inductance generated at a time of semiconductor packaging and automating the entire process of the semiconductor packaging.
-
公开(公告)号：US20170117889A1
公开(公告)日：2017-04-27
申请号：US15223826
申请日：2016-07-29
Inventor： Minki KIM , Hyun-Gyu JANG , Dong Yun JUNG , Sang Choon KO , Hyun Soo LEE , Chi Hoon JUN
IPC: H03K17/081 , H01L27/088 , H01L29/20 , H01L29/778
CPC classification number: H03K17/08104 , H01L27/0883 , H01L29/2003 , H01L29/41758 , H01L29/42316 , H01L29/778 , H01L29/7786 , H03K17/102 , H03K2017/6875
Abstract: Provided is a stabilizing circuit structure using a sense field effect transistor (sense-FET). A power semiconductor module includes a depletion-mode field effect transistor (D-mode FET) and the sense FET that has same structure as the D-mode FET and varies in area. Also the power semiconductor module includes not only an enhancement-mode field effect transistor (E-mode FET), but also the stabilizing circuit including circuit elements such as a resistor, a capacitor, an inductor, or a diode.
-
Patent Agency Ranking
公开(公告)号：US20170025550A1
公开(公告)日：2017-01-26
申请号：US15215414
申请日：2016-07-20
Inventor： Dong Yun JUNG , Hyun Soo LEE , Sang Choon KO , Minki KIM , Jeho NA , EUN SOO NAM , Young Rak PARK , Junbo PARK , Hyung Seok LEE , Hyun-Gyu JANG , Chi Hoon JUN
IPC: H01L29/861 , H01L29/205
CPC classification number: H01L29/205 , H01L29/2003 , H01L29/66212 , H01L29/872
Abstract: Provided is a bridge diode according to an embodiment of the inventive concept. The bridge diode includes a first structure including a first lower nitride film and a first upper nitride film, which are laminated on the substrate, a second structure including a second lower nitride film and a second upper nitride film, which are laminated on the substrate, a first electrode structural body disposed on the first structure, and a second electrode structural body disposed on the second structure. The first electrode structural body includes a first electrode, a second electrode, and a third electrode, which are arranged in a clockwise direction, the second electrode structural body includes a fourth electrode, a fifth electrode, and a sixth electrode, which are arranged in a clockwise direction, the first electrode and the sixth electrode, which are connected to each other, are connected to an external circuit, the third electrode and the fourth electrode, which are connected to each other, are connected to an external circuit, and each of the second electrode and the fifth electrode is connected to the external circuit.
Abstract translation: 提供根据本发明构思的实施例的桥式二极管。 桥式二极管包括层叠在基板上的第一下部氮化物膜和第一上部氮化物膜的第一结构，包括层叠在基板上的第二下部氮化物膜和第二上部氮化物膜的第二结构， 设置在第一结构上的第一电极结构体和设置在第二结构上的第二电极结构体。 第一电极结构体包括沿顺时针方向布置的第一电极，第二电极和第三电极，第二电极结构体包括第四电极，第五电极和第六电极，其布置在 连接到彼此连接的顺时针方向，第一电极和第六电极连接到彼此连接的外部电路，第三电极和第四电极连接到外部电路，并且每个 的第二电极和第五电极连接到外部电路。
-
公开(公告)号：US20230087416A1
公开(公告)日：2023-03-23
申请号：US17792070
申请日：2021-06-10
Inventor： Kun Sik PARK , Jong II WON , Doo Hyung CHO , Dong Yun JUNG , Hyun GYu Jang
IPC: H01L29/745 , H01L29/08 , H01L29/10 , H01L29/66
Abstract: A MOS controlled thyristor device according to the concept of the present invention includes a substrate comprising a first surface and a second surface, which face each other, gate patterns disposed on the first surface, a cathode electrode configured to cover the gate patterns, and an anode electrode disposed on the second surface, The substrate includes a lower emitter layer having a first conductive type, a lower base layer having a second conductive type on the lower emitter layer, an upper base region provided in an upper portion of the lower emitter layer and having a first conductive type, wherein the upper base region is configured to expose a portion of a top surface of the lower base layer, an upper emitter region having a second conductive type and provided in an upper portion of the upper base region, a first doped region having a first conductive type and a second doped region surrounded by the first doped region and having a second conductive type, wherein the first and second doped regions are provided in an upper portion of the upper emitter region, and a first doping pattern having a first conductive type, which is provided on one surface of the upper portion of the upper emitter region. The first doping pattern is interposed between the upper base region and the first doped region along a first direction parallel to the top surface of the substrate. The first doping pattern is configured to expose a top surface of the upper emitter region on the other surface of the upper portion of the upper emitter region. Each of the gate patterns is configured to cover portions of an exposed top surface of the lower base layer, an exposed top surface of the upper base layer, an exposed top surface of the upper emitter region, a top surface of the first doping pattern, and a top surface of the first doped region. The cathode electrode is configured to cover portions of top and side surfaces of the gate pattern, a top surface of the second doped region, and a top surface of the first doped region. The first conductive type and the second conductive type are different from each other.
-
公开(公告)号：US20210408265A1
公开(公告)日：2021-12-30
申请号：US17355977
申请日：2021-06-23
Inventor： Kun Sik PARK , Jong Il WON , Doo Hyung CHO , Hyun Gyu JANG , Dong Yun JUNG
IPC: H01L29/66 , H01L29/745 , H01L29/749
Abstract: The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.
-
公开(公告)号：US20190097513A1
公开(公告)日：2019-03-28
申请号：US16122631
申请日：2018-09-05
Inventor： Minki KIM , Junbo PARK , Dong Yun JUNG
Abstract: The present disclosure relates to a spherical wheel motor and a control system thereof, and more particularly, the spherical wheel motor and the control system include a spherical rotor and a stator surrounding an upper surface of the rotor. The rotor includes a spherical outer shell part, a first axial magnet extending in a horizontal direction in the outer shell part, a second axial magnet extending in the horizontal direction and facing the first axial magnet, and a rotary magnet belt provided in a form of a belt with the first axial magnet and the second axial magnet as a central axis. The rotary magnet belt includes a plurality of first rotary magnets and a plurality of second rotary magnets arranged alternately.
-
公开(公告)号：US20170062385A1
公开(公告)日：2017-03-02
申请号：US15221089
申请日：2016-07-27
Inventor： Dong Yun JUNG , Sang Choon KO , Chi Hoon JUN , Minki KIM , Jeho NA , EUN SOO NAM , Young Rak PARK , Junbo PARK , Hyun Soo LEE , Hyung Seok LEE , Hyun-Gyu JANG
IPC: H01L25/065 , H01L29/78 , H01L23/522 , H01L23/528 , H02M3/158 , H01L23/373
CPC classification number: H01L25/0652 , H01L23/367 , H01L23/3736 , H01L23/4012 , H01L23/49822 , H01L23/50 , H01L23/5226 , H01L23/528 , H01L25/072 , H01L29/78 , H02M3/156
Abstract: Disclosed is a power converting device including: a first laminate having a plurality of non-magnetic substrates which are laminated; electronic devices disposed on at least one of the non-magnetic substrates; first conductive patterns disposed on the non-magnetic substrate on which the electronic devices are disposed, the first conductive patterns being connected to the electronic devices; at least one via electrode connecting the respective first conductive patterns to each other; a second laminate disposed on one side of the first laminate and having a plurality of magnetic sheets which are laminated; second conductive patterns disposed on at least two magnetic sheets among the plurality of magnetic sheets; and at least one via electrode connecting the respective second conductive patterns to each other, wherein the first and second via electrodes are connected to each other.
Abstract translation: 公开了一种电力转换装置，包括：第一层压体，其具有层叠的多个非磁性基板; 设置在所述非磁性基板中的至少一个上的电子设备; 布置在其上设置有电子设备的非磁性基板上的第一导电图案，第一导电图案连接到电子设备; 将相应的第一导电图案彼此连接的至少一个通孔电极; 第二层压体，其设置在所述第一层叠体的一侧，并且具有层叠的多个磁性片; 设置在所述多个磁性片中的至少两个磁性片上的第二导电图案; 以及将各个第二导电图案彼此连接的至少一个通孔电极，其中所述第一和第二通孔电极彼此连接。
-
-
-
-
-
-
-
-
-
Search Results
15
records
(took 0.036 seconds)
