公开(公告)号：US20210335681A1

公开(公告)日：2021-10-28

申请号：US17217433

申请日：2021-03-30

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hyun Gyu JANG ,  Dong Yun JUNG ,  Doo Hyung CHO ,  Kun Sik PARK ,  Jong Won LIM

IPC: H01L23/15 ,  H01L25/065 ,  H01L23/31 ,  H01L21/768 ,  H01L23/538 ,  H01L21/48

Abstract: A ceramic stacked semiconductor package and a method of packaging a ceramic stacked semiconductor is disclosed. Inner walls of junctions are formed between ceramic layers and a molding resin to have a non-uniform boundary shape (e.g., Z shape, an uneven shape, a zigzag shape, etc.) so that bonding areas and lengths of the molding resin and the ceramic layers are increased, and thus adhesion is improved and movement paths of moisture are increased, thereby improving anti-humidity property and reliability of the semiconductor package. Further, by arranging via-holes at different positions for each layer so as not to overlap each other between the layers, movement paths of moisture passing through the via-holes are increased, and thus the anti-humidity property and reliability of the stacked package are additionally improved.

公开(公告)号：US20220020671A1

公开(公告)日：2022-01-20

申请号：US17380583

申请日：2021-07-20

Applicant: Electronics and Telecommunications Research Institute

Inventor： Dong Yun JUNG ,  Hyun Gyu JANG ,  Sung Kyu KWON ,  Kun Sik PARK ,  Jong Il WON ,  Seong Hyun LEE ,  Jong Won LIM ,  Doo Hyung CHO

IPC: H01L23/495 ,  H01L23/00

Abstract: The present invention minimizes parasitic inductance at the time of packaging a semiconductor that requires high efficiency and high-speed switching driving. In implementing a semiconductor package composed of one or more switching devices and one or more diode devices, the present invention provides a flip-stack structure in which a switching device is mounted on an insulating substrate or a metal frame, a flat metal is bonded onto the switching device, and a diode device is flipped and stacked on the flat metal, and accordingly, the flat metal with a large area is used for connection between the devices and between the devices and the insulating substrate, thereby minimizing parasitic inductance generated at a time of semiconductor packaging and automating the entire process of the semiconductor packaging.

公开(公告)号：US20230087416A1

公开(公告)日：2023-03-23

申请号：US17792070

申请日：2021-06-10

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Kun Sik PARK ,  Jong II WON ,  Doo Hyung CHO ,  Dong Yun JUNG ,  Hyun GYu Jang

IPC: H01L29/745 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: A MOS controlled thyristor device according to the concept of the present invention includes a substrate comprising a first surface and a second surface, which face each other, gate patterns disposed on the first surface, a cathode electrode configured to cover the gate patterns, and an anode electrode disposed on the second surface, The substrate includes a lower emitter layer having a first conductive type, a lower base layer having a second conductive type on the lower emitter layer, an upper base region provided in an upper portion of the lower emitter layer and having a first conductive type, wherein the upper base region is configured to expose a portion of a top surface of the lower base layer, an upper emitter region having a second conductive type and provided in an upper portion of the upper base region, a first doped region having a first conductive type and a second doped region surrounded by the first doped region and having a second conductive type, wherein the first and second doped regions are provided in an upper portion of the upper emitter region, and a first doping pattern having a first conductive type, which is provided on one surface of the upper portion of the upper emitter region. The first doping pattern is interposed between the upper base region and the first doped region along a first direction parallel to the top surface of the substrate. The first doping pattern is configured to expose a top surface of the upper emitter region on the other surface of the upper portion of the upper emitter region. Each of the gate patterns is configured to cover portions of an exposed top surface of the lower base layer, an exposed top surface of the upper base layer, an exposed top surface of the upper emitter region, a top surface of the first doping pattern, and a top surface of the first doped region. The cathode electrode is configured to cover portions of top and side surfaces of the gate pattern, a top surface of the second doped region, and a top surface of the first doped region. The first conductive type and the second conductive type are different from each other.

公开(公告)号：US20210408265A1

公开(公告)日：2021-12-30

申请号：US17355977

申请日：2021-06-23

Applicant: Electronics and Telecommunications Research Institute

Inventor： Kun Sik PARK ,  Jong Il WON ,  Doo Hyung CHO ,  Hyun Gyu JANG ,  Dong Yun JUNG

IPC: H01L29/66 ,  H01L29/745 ,  H01L29/749

Abstract: The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.

公开(公告)号：US20220299554A1

公开(公告)日：2022-09-22

申请号：US17510856

申请日：2021-10-26

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Dong Yun JUNG ,  Hyun Gyu JANG ,  Kun Sik PARK ,  JONG IL WON ,  Sung Kyu KWON ,  Jong Won LIM ,  Doo Hyung CHO

IPC: G01R31/00

Abstract: The apparatus for ESD test includes a micro-controller unit client, a low voltage supply configured to output a low voltage on the basis of control by the micro-controller unit, a high voltage supply configured to output a high voltage on the basis of control by the micro-controller unit, and an ESD generator configured to generate an ESD voltage for an ESD test of a device under test (DUT) by using the low voltage and the high voltage, on the basis of control by the micro-controller unit. The ESD generator is a semiconductor integrated circuit module where a charging semiconductor switch, a discharging semiconductor switch, a switch driving block controlling a switching operation of each of the charging semiconductor switch and the discharging semiconductor switch, and a plurality of passive elements connected to the charging semiconductor switch and the discharging semiconductor switch are implemented as package, for generating the ESD voltage.

公开(公告)号：US20160284872A1

公开(公告)日：2016-09-29

申请号：US15080338

申请日：2016-03-24

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Kun Sik PARK ,  Jong II WON ,  Doo Hyung CHO

IPC: H01L29/872 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L29/872 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/417 ,  H01L29/6606

Abstract: Provided is a Schottky diode including a substrate, a drift layer on the substrate, the drift layer comprising an active region and a periphery positioned at an edge of the active region, a junction termination layer on a boundary between the active region and the periphery, a first metal layer configured to cover a part of the active region and a part of the junction termination layer, and a second metal layer configured to cover the first metal layer and the active region, wherein the first metal layer and the second metal layer contact the drift layer to provide a Schottky junction, and the first metal layer has a higher Schottky barrier height than the second metal layer.

Abstract translation: 提供了一种肖特基二极管，其包括衬底，衬底上的漂移层，漂移层包括有源区和位于有源区的边缘处的周边，活性区和周边之间的边界上的结终端层， 第一金属层，其被配置为覆盖所述有源区的一部分和所述结终端层的一部分;以及第二金属层，被配置为覆盖所述第一金属层和所述有源区，其中所述第一金属层和所述第二金属层接触 所述漂移层提供肖特基结，并且所述第一金属层具有比所述第二金属层更高的肖特基势垒高度。