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公开(公告)号：US20210335681A1
公开(公告)日：2021-10-28
申请号：US17217433
申请日：2021-03-30
Inventor： Hyun Gyu JANG , Dong Yun JUNG , Doo Hyung CHO , Kun Sik PARK , Jong Won LIM
IPC: H01L23/15 , H01L25/065 , H01L23/31 , H01L21/768 , H01L23/538 , H01L21/48
Abstract: A ceramic stacked semiconductor package and a method of packaging a ceramic stacked semiconductor is disclosed. Inner walls of junctions are formed between ceramic layers and a molding resin to have a non-uniform boundary shape (e.g., Z shape, an uneven shape, a zigzag shape, etc.) so that bonding areas and lengths of the molding resin and the ceramic layers are increased, and thus adhesion is improved and movement paths of moisture are increased, thereby improving anti-humidity property and reliability of the semiconductor package. Further, by arranging via-holes at different positions for each layer so as not to overlap each other between the layers, movement paths of moisture passing through the via-holes are increased, and thus the anti-humidity property and reliability of the stacked package are additionally improved.
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公开(公告)号：US20210408265A1
公开(公告)日：2021-12-30
申请号：US17355977
申请日：2021-06-23
Inventor： Kun Sik PARK , Jong Il WON , Doo Hyung CHO , Hyun Gyu JANG , Dong Yun JUNG
IPC: H01L29/66 , H01L29/745 , H01L29/749
Abstract: The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.
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公开(公告)号：US20220020671A1
公开(公告)日：2022-01-20
申请号：US17380583
申请日：2021-07-20
Inventor： Dong Yun JUNG , Hyun Gyu JANG , Sung Kyu KWON , Kun Sik PARK , Jong Il WON , Seong Hyun LEE , Jong Won LIM , Doo Hyung CHO
IPC: H01L23/495 , H01L23/00
Abstract: The present invention minimizes parasitic inductance at the time of packaging a semiconductor that requires high efficiency and high-speed switching driving. In implementing a semiconductor package composed of one or more switching devices and one or more diode devices, the present invention provides a flip-stack structure in which a switching device is mounted on an insulating substrate or a metal frame, a flat metal is bonded onto the switching device, and a diode device is flipped and stacked on the flat metal, and accordingly, the flat metal with a large area is used for connection between the devices and between the devices and the insulating substrate, thereby minimizing parasitic inductance generated at a time of semiconductor packaging and automating the entire process of the semiconductor packaging.
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公开(公告)号：US20220299554A1
公开(公告)日：2022-09-22
申请号：US17510856
申请日：2021-10-26
Inventor： Dong Yun JUNG , Hyun Gyu JANG , Kun Sik PARK , JONG IL WON , Sung Kyu KWON , Jong Won LIM , Doo Hyung CHO
IPC: G01R31/00
Abstract: The apparatus for ESD test includes a micro-controller unit client, a low voltage supply configured to output a low voltage on the basis of control by the micro-controller unit, a high voltage supply configured to output a high voltage on the basis of control by the micro-controller unit, and an ESD generator configured to generate an ESD voltage for an ESD test of a device under test (DUT) by using the low voltage and the high voltage, on the basis of control by the micro-controller unit. The ESD generator is a semiconductor integrated circuit module where a charging semiconductor switch, a discharging semiconductor switch, a switch driving block controlling a switching operation of each of the charging semiconductor switch and the discharging semiconductor switch, and a plurality of passive elements connected to the charging semiconductor switch and the discharging semiconductor switch are implemented as package, for generating the ESD voltage.
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