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公开(公告)号：US20210335681A1
公开(公告)日：2021-10-28
申请号：US17217433
申请日：2021-03-30
Inventor： Hyun Gyu JANG , Dong Yun JUNG , Doo Hyung CHO , Kun Sik PARK , Jong Won LIM
IPC: H01L23/15 , H01L25/065 , H01L23/31 , H01L21/768 , H01L23/538 , H01L21/48
Abstract: A ceramic stacked semiconductor package and a method of packaging a ceramic stacked semiconductor is disclosed. Inner walls of junctions are formed between ceramic layers and a molding resin to have a non-uniform boundary shape (e.g., Z shape, an uneven shape, a zigzag shape, etc.) so that bonding areas and lengths of the molding resin and the ceramic layers are increased, and thus adhesion is improved and movement paths of moisture are increased, thereby improving anti-humidity property and reliability of the semiconductor package. Further, by arranging via-holes at different positions for each layer so as not to overlap each other between the layers, movement paths of moisture passing through the via-holes are increased, and thus the anti-humidity property and reliability of the stacked package are additionally improved.
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公开(公告)号：US20150349736A1
公开(公告)日：2015-12-03
申请号：US14666163
申请日：2015-03-23
Inventor： Sang Heung LEE , Dong Min KANG , SEONG IL KIM , Ho Kyun AHN , Hyung Sup YOON , Jong Won LIM , Chull Won JU
CPC classification number: H03G1/0088 , H03F1/083 , H03F3/08 , H03F2200/153 , H03G3/12
Abstract: Provided herein is a feedback amplifier including an amplifier circuit configured to amplify an input signal input from an input terminal and output the amplified input signal to an output terminal; a feedback circuit configured to apply a feedback resistance value to a signal output to the output terminal, and to control a gain of the amplifier circuit by adjusting the input signal by a bias voltage applied with a feedback resistance value determined; a packet signal sensor configured to generate a fixed resistance control signal for controlling a fixed resistance value included in the feedback resistance value through a comparison between the output from the output terminal with a minimum signal level; and a fixed resistance controller configured to control the fixed resistance value included in the feedback resistance value in response to the fixed resistance control signal.
Abstract translation: 本文提供了一种反馈放大器，包括：放大器电路，被配置为放大从输入端输入的输入信号，并将放大的输入信号输出到输出端; 反馈电路，被配置为向输出端子输出的信号施加反馈电阻值，并且通过利用所确定的反馈电阻值施加的偏置电压来调节所述输入信号来控制所述放大器电路的增益; 分组信号传感器，被配置为通过比较来自所述输出端子的输出与最小信号电平之间的比较，产生用于控制所述反馈电阻值中包括的固定电阻值的固定电阻控制信号; 以及固定电阻控制器，其被配置为响应于所述固定电阻控制信号来控制包括在所述反馈电阻值中的所述固定电阻值。
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3.发明申请GaN TRANSISTOR WITH IMPROVED BONDING PAD STRUCTURE AND METHOD OF FABRICATING THE SAME 有权具有改进的粘结片结构的GaN晶体管及其制造方法公开(公告)号：US20150206847A1
公开(公告)日：2015-07-23
申请号：US14453969
申请日：2014-08-07
Inventor： Hae Cheon KIM , Ho Kyun AHN , Byoung Gue MIN , Hyung Sup YOON , Jong Won LIM
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L24/03 , H01L24/48 , H01L2224/0225 , H01L2224/03466 , H01L2224/03848 , H01L2224/0401 , H01L2224/04042 , H01L2224/05083 , H01L2224/05084 , H01L2224/05124 , H01L2224/05144 , H01L2224/05155 , H01L2224/05166 , H01L2224/05644 , H01L2224/48463 , H01L2924/00014 , H01L2924/10158 , H01L2924/1033 , H01L2924/1304 , H01L2924/13091 , H01L2924/1423 , H01L2924/201 , H01L2924/37001 , H01L2224/45099
Abstract: The present invention relates to a GaN transistor, and a method of fabricating the same, in which a structure of a bonding pad is improved by forming an ohmic metal layer at edges of the bonding pad of a source, a drain, and a gate so as to be appropriate to wire-bonding or a back-side via-hole forming process. Accordingly, adhesive force between a metal layer of the bonding pad and a GaN substrate is enhanced by forming the ohmic metal at the edges of the bonding pad during manufacturing of the GaN transistor, thereby minimizing a separation phenomenon of a pad layer during the wire-bonding or back-side via-hole forming process, and improving reliability of a device.
Abstract translation: 本发明涉及一种GaN晶体管及其制造方法，其中通过在源极，漏极和栅极的焊盘的边缘处形成欧姆金属层来改善焊盘的结构，因此 适于引线接合或背面通孔形成工艺。 因此，通过在制造GaN晶体管期间在焊盘的边缘处形成欧姆金属，可以增强焊盘的金属层与GaN基板之间的粘合力， 接合或背面通孔形成工艺，并提高器件的可靠性。
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公开(公告)号：US20150380482A1
公开(公告)日：2015-12-31
申请号：US14658121
申请日：2015-03-13
Inventor： Ho Kyun AHN , Hae Cheon KIM , Jong Won LIM , Dong Min KANG , Yong Hwan KWON , SEONG IL KIM , Zin Sig KIM , Eun Soo NAM , Byoung Gue MIN , Hyung Sup YOON , Kyung Ho LEE , Jong Min LEE , Kyu Jun CHO
IPC: H01L29/06 , H01L29/66 , H01L29/205 , H01L29/20 , H01L21/28 , H01L29/49 , H01L29/423 , H01L21/02 , H01L21/311 , H01L21/31 , H01L29/778 , H01L29/45
CPC classification number: H01L21/28264 , H01L29/2003 , H01L29/407 , H01L29/42316 , H01L29/4236 , H01L29/452 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/7786
Abstract: Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.
Abstract translation: 本文提供了包括基板的半导体器件; 形成在所述基板的顶部上的有源层; 形成在所述有源层的顶部上并具有第一孔的保护层; 源电极，形成在保护层顶部的驱动栅电极和漏电极; 以及形成在所述第一孔的顶部上的第一附加栅电极，其中由于施加到所述源电极，漏电极和驱动栅电极中的每一个的电压，向所述有源层，保护层和驱动栅电极施加电场， 并且第一附加栅电极被配置为衰减施加到有源层，保护层和驱动栅电极的至少一部分的电场的尺寸。
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公开(公告)号：US20150270822A1
公开(公告)日：2015-09-24
申请号：US14478295
申请日：2014-09-05
Inventor： Dong Min KANG , Seong Il KIM , Sang Heung LEE , Chull Won JU , Ho Kyun AHN , Hyung Sup YOON , Jong Won LIM
IPC: H03H7/38
CPC classification number: H03H7/38 , H01L23/642 , H01L2224/49175 , H01P1/2039 , H01P5/12 , H05K1/025 , H05K2201/09781
Abstract: Provided herein is a component package including a matching unit and a matching method thereof, the matching unit including: a substrate; a transmission line formed on the substrate, the transmission line being connected to a terminal of the component package; a bonding wire electrically connecting the transmission line and a central component; and a capacitor unit having a plurality of capacitors electrically connected with the transmission line by wiring connection, wherein an inductance of the matching unit is variable by adjusting a length of the bonding wire, and a capacitance of the matching unit is variable by increasing or reducing the number of capacitors electrically connected to the transmission line, of among the capacitors inside the capacitor unit, by extending or cutting off the wiring connection.
Abstract translation: 本文提供了一种包括匹配单元及其匹配方法的组件封装，所述匹配单元包括：衬底; 形成在所述基板上的传输线，所述传输线连接到所述部件封装的端子; 电连接所述传输线和中心部件的接合线; 以及具有通过布线连接与传输线电连接的多个电容器的电容器单元，其中匹配单元的电感通过调整接合线的长度而变化，并且匹配单元的电容可通过增加或减小而变化 通过延长或切断布线连接，在电容器单元内的电容器之间电连接到传输线的电容器的数量。
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Patent Agency Ranking
6.发明申请FIELD-EFFECT TRANSISTOR FOR HIGH VOLTAGE DRIVING AND MANUFACTURING METHOD THEREOF 审中-公开用于高压驱动的场效应晶体管及其制造方法公开(公告)号：US20150194494A1
公开(公告)日：2015-07-09
申请号：US14243322
申请日：2014-04-02
Inventor： Ho Kyun AHN , Hae Cheon KIM , Zin Sig KIM , Sang Heung LEE , Byoung Gue MIN , Hyung Sup YOON , Dong Min KANG , Seong Il KIM , Jong Min LEE , Jong Won LIM , Yong Hwan KWON , Eun Soo NAM
IPC: H01L29/40 , H01L29/66 , H01L21/28 , H01L21/283 , H01L29/78 , H01L29/423
CPC classification number: H01L29/402 , H01L21/283 , H01L21/28593 , H01L29/2003 , H01L29/42312 , H01L29/42356 , H01L29/66462 , H01L29/66477 , H01L29/7787
Abstract: Disclosed are a field effect transistor for high voltage driving including a gate electrode structure in which a gate head extended in a direction of a drain is supported by a field plate embedded under a region of the gate head so as to achieve high voltage driving, and a manufacturing method thereof. Accordingly, the gate head extended in the direction of the drain is supported by the field plate electrically spaced by using an insulating layer, so that it is possible to stably manufacture a gate electrode including the extended gate head, and gate resistance is decreased by the gate head extended in the direction of the drain and an electric field peak value between the gate and the drain is decreased by the gate electrode including the gate head extended in the direction of the drain and the field plate proximate to the gate, thereby achieving an effect in that a breakdown voltage of a device is increased.
Abstract translation: 公开了一种用于高电压驱动的场效应晶体管，其包括栅极电极结构，其中在漏极方向上延伸的栅极头由嵌入在栅极头的区域内的场板支撑以实现高电压驱动，以及 其制造方法。 因此，在漏极方向上延伸的栅极头通过使用绝缘层而被电隔离的场板支撑，使得可以稳定地制造包括延伸栅极头的栅电极，并且栅极电阻通过 栅极头在漏极的方向上延伸，栅极和漏极之间的电场峰值由包括在漏极方向上延伸的栅极和靠近栅极的场板的栅电极减小，由此实现 效果是器件的击穿电压增加。
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公开(公告)号：US20150144961A1
公开(公告)日：2015-05-28
申请号：US14175452
申请日：2014-02-07
Inventor： Hyung Sup YOON , Byoung Gue MIN , Ho Kyun AHN , Jong Won LIM , Dong Min KANG , Jong Min LEE
IPC: H01L29/778 , H01L29/45 , H01L29/66
CPC classification number: H01L29/42316 , H01L29/2003 , H01L29/452 , H01L29/66462 , H01L29/7786
Abstract: A high frequency device includes: a capping layer formed on an epitaxial structure; source and drain electrodes formed on the capping layer; a multilayer insulating pattern formed on entire surfaces of the source and drain electrodes and the capping layer in a step shape; a T-shaped gate passing through the multilayer insulating pattern and the capping layer to be in contact with the epitaxial structure; and a passivation layer formed along entire surfaces of the T-shaped gate and the multilayer insulating pattern.
Abstract translation: 高频器件包括：形成在外延结构上的覆盖层; 源极和漏极形成在覆盖层上; 形成在所述源电极和漏电极以及所述覆盖层的整个表面上的阶梯形状的多层绝缘图案; 通过所述多层绝缘图案和所述覆盖层与所述外延结构接触的T形栅极; 以及在T形栅极和多层绝缘图案的整个表面上形成的钝化层。
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公开(公告)号：US20220299554A1
公开(公告)日：2022-09-22
申请号：US17510856
申请日：2021-10-26
Inventor： Dong Yun JUNG , Hyun Gyu JANG , Kun Sik PARK , JONG IL WON , Sung Kyu KWON , Jong Won LIM , Doo Hyung CHO
IPC: G01R31/00
Abstract: The apparatus for ESD test includes a micro-controller unit client, a low voltage supply configured to output a low voltage on the basis of control by the micro-controller unit, a high voltage supply configured to output a high voltage on the basis of control by the micro-controller unit, and an ESD generator configured to generate an ESD voltage for an ESD test of a device under test (DUT) by using the low voltage and the high voltage, on the basis of control by the micro-controller unit. The ESD generator is a semiconductor integrated circuit module where a charging semiconductor switch, a discharging semiconductor switch, a switch driving block controlling a switching operation of each of the charging semiconductor switch and the discharging semiconductor switch, and a plurality of passive elements connected to the charging semiconductor switch and the discharging semiconductor switch are implemented as package, for generating the ESD voltage.
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公开(公告)号：US20150207233A1
公开(公告)日：2015-07-23
申请号：US14337907
申请日：2014-07-22
Inventor： Dong Young KIM , Jong Won LIM , Cheon Soo KIM
CPC classification number: H01Q9/0485
Abstract: Disclosed is a dielectric resonator antenna. The dielectric resonator antenna includes: a dielectric resonator; an antenna layer formed inside the dielectric resonator, and including a plurality of vias positioned at a surrounding area of the dielectric resonator; a metal pattern forming an opened surface in an upper portion of the antenna layer; a dielectric layer configured to cover the metal pattern on the dielectric resonator; an internal ground pattern including a coupling aperture for inputting a signal into the dielectric resonator under the dielectric resonator; and a feeding layer including a strip transmission line for transmitting a signal to the dielectric resonator, and positioned under the antenna layer.
Abstract translation: 公开了一种介质谐振器天线。 介质谐振器天线包括：介质谐振器; 形成在介质谐振器内的天线层，并且包括位于介电谐振器的周围区域的多个通孔; 金属图案，在天线层的上部形成开放面; 介电层，被配置为覆盖介质谐振器上的金属图案; 内部接地图案，包括用于将信号输入介质谐振器下的介质谐振器的耦合孔; 以及馈电层，其包括用于将信号传输到介质谐振器并位于天线层下方的带状传输线。
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公开(公告)号：US20230054026A1
公开(公告)日：2023-02-23
申请号：US17891832
申请日：2022-08-19
Inventor： Hyun Wook JUNG , Seong II KIM , Hae Cheon KIM , Youn Sub NOH , Ho Kyun AHN , Sang Heung LEE , Jong Won LIM , Sung Jae CHANG , II Gyu CHOI
IPC: H01L29/778 , H01L29/66 , H01L29/423 , H01L29/40
Abstract: Provided are a nitride-based high electron mobility transistor having enhanced frequency characteristics and an improved structural stability and manufacturing method thereof. The nitride-based high electron mobility transistor includes a first semiconductor layer and a second semiconductor layer sequentially formed on a substrate, source drain electrodes formed on the second semiconductor layer, a first insulating film formed on the second semiconductor layer and having an opening, a dielectric formed on the first insulating film to surround the opening of the first insulating film, a second insulating film formed on an inner sidewall of the dielectric, and a gate electrode formed on the dielectric to fill the opening of the first insulating film and inside the inner sidewall of the dielectric. A width of the inner sidewall at a bottom end of the dielectric is smaller than a width of the inner sidewall at a top end of the dielectric.
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