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Patent Agency Ranking
公开(公告)号：US20170133471A1
公开(公告)日：2017-05-11
申请号：US15238492
申请日：2016-08-16
Inventor： Jong Min LEE , Byoung-Gue MIN , Hyung Sup YOON , Dong Min KANG , Dong-Young KIM , SEONG-IL KIM , Hae Cheon KIM , Jae Won DO , Ho Kyun AHN , Sang-Heung LEE , Jong-Won LIM , Hyun Wook JUNG , Kyu Jun CHO , Chull Won JU
IPC: H01L29/40 , H01L29/66 , H01L29/778 , H01L29/20 , H01L29/205
CPC classification number: H01L29/408 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7786 , H01L29/7787
Abstract: The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.
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公开(公告)号：US20210083632A1
公开(公告)日：2021-03-18
申请号：US16941691
申请日：2020-07-29
Inventor： Woojin CHANG , SEONG-IL KIM , Sang-Heung LEE , Jongmin LEE
Abstract: Provided is an amplification circuit for amplifying an input signal. The amplification circuit includes an input stage including an input matching circuit that receives the input signal and an input attenuation circuit that attenuates a gain for the input signal outside an operating frequency band of the amplification circuit, a transistor that amplifies the input signal provided from the input stage, and an output stage including an output matching circuit that receives a signal amplified by the transistor and an output attenuation circuit that attenuates the gain for the input signal outside the operating frequency band of the amplification circuit, and the input attenuation circuit includes a first resistor and a second resistor that are connected to a ground voltage, a first passive element connected between the input matching circuit and the second resistor, and a second passive element connected between the first passive element and the first resistor.
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公开(公告)号：US20190103483A1
公开(公告)日：2019-04-04
申请号：US16137235
申请日：2018-09-20
Inventor： Hokyun AHN , Min Jeong SHIN , Jeong Jin KIM , Hae Cheon KIM , Jae Won DO , Byoung-Gue MIN , Hyung Sup YOON , Hyung Seok LEE , Jong-Won LIM , Sungjae CHANG , Hyunwook JUNG , Kyu Jun CHO , Dong Min KANG , Dong-Young KIM , SEONG-IL KIM , Sang-Heung LEE , Jongmin LEE , Hong Gu JI
IPC: H01L29/78 , H01L29/20 , H01L29/45 , H01L29/417 , H01L29/423 , H01L29/66 , H01L21/3065
Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.
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公开(公告)号：US20190081166A1
公开(公告)日：2019-03-14
申请号：US16028612
申请日：2018-07-06
Inventor： Jae Won DO , Dong Min KANG , Dong-Young KIM , SEONG-IL KIM , Hae Cheon KIM , Byoung-Gue MIN , Min Jeong SHIN , Hokyun AHN , Hyung Sup YOON , Sang-Heung LEE , Jongmin LEE , Jong-Won LIM , Sungjae CHANG , Yoo Jin JANG , Hyunwook JUNG , Kyu Jun CHO , Hong Gu JI
IPC: H01L29/778 , H01L29/423 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/205
Abstract: Provided is a gate-all-around device. The gate-all-around device includes a substrate, a pair of heterojunction source/drain regions provided on the substrate, a heterojunction channel region provided between the pair of heterojunction source/drain regions, and a pair of ohmic electrodes provided on the pair of heterojunction source/drain regions, respectively. Each of the pair of heterojunction source/drain regions includes a pair of two-dimensional electron gas layers. The pair of ohmic electrodes extends toward an upper surface of the substrate and pass through the pair of heterojunction source/drain regions, respectively.
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公开(公告)号：US20170237171A1
公开(公告)日：2017-08-17
申请号：US15229891
申请日：2016-08-05
Inventor： Dong-Young KIM , Dong Min KANG , SEONG-IL KIM , Hae Cheon KIM , Jae Won DO , Byoung-Gue MIN , Ho Kyun AHN , Hyung Sup YOON , Sang-Heung LEE , Jong Min LEE , Jong-Won LIM , Yoo Jin JANG , Hyun Wook JUNG , Kyu Jun CHO , Chull Won JU
CPC classification number: H01Q9/0407 , H01Q1/50 , H01Q9/0442
Abstract: Provided herein is a patch antenna including a multilayered substrate on which a plurality of dielectric layers are laminated; at least one metal pattern layer disposed between the plurality of dielectric layers outside a central area of the multilayered substrate; an antenna patch disposed on an upper surface of the multilayered substrate and within the central area; a ground layer disposed on a lower surface of the multilayered substrate; a plurality of connection via patterns penetrating the plurality of dielectric layers to connect the metal pattern layer and the ground layer, and surrounding the central area; a transmission line comprising a first transmission line unit disposed on the upper surface of the multilayered substrate and located outside the central area, and a second transmission line unit disposed on the upper surface of the multilayered substrate and located within the central area; and an impedance transformer located below the second transmission line unit within the central area of the multilayered substrate.
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