公开(公告)号：US20190103483A1

公开(公告)日：2019-04-04

申请号：US16137235

申请日：2018-09-20

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Hokyun AHN ,  Min Jeong SHIN ,  Jeong Jin KIM ,  Hae Cheon KIM ,  Jae Won DO ,  Byoung-Gue MIN ,  Hyung Sup YOON ,  Hyung Seok LEE ,  Jong-Won LIM ,  Sungjae CHANG ,  Hyunwook JUNG ,  Kyu Jun CHO ,  Dong Min KANG ,  Dong-Young KIM ,  SEONG-IL KIM ,  Sang-Heung LEE ,  Jongmin LEE ,  Hong Gu JI

IPC分类号： H01L29/78 ,  H01L29/20 ,  H01L29/45 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3065

摘要： Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.

公开(公告)号：US20190081166A1

公开(公告)日：2019-03-14

申请号：US16028612

申请日：2018-07-06

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Jae Won DO ,  Dong Min KANG ,  Dong-Young KIM ,  SEONG-IL KIM ,  Hae Cheon KIM ,  Byoung-Gue MIN ,  Min Jeong SHIN ,  Hokyun AHN ,  Hyung Sup YOON ,  Sang-Heung LEE ,  Jongmin LEE ,  Jong-Won LIM ,  Sungjae CHANG ,  Yoo Jin JANG ,  Hyunwook JUNG ,  Kyu Jun CHO ,  Hong Gu JI

IPC分类号： H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/205

摘要： Provided is a gate-all-around device. The gate-all-around device includes a substrate, a pair of heterojunction source/drain regions provided on the substrate, a heterojunction channel region provided between the pair of heterojunction source/drain regions, and a pair of ohmic electrodes provided on the pair of heterojunction source/drain regions, respectively. Each of the pair of heterojunction source/drain regions includes a pair of two-dimensional electron gas layers. The pair of ohmic electrodes extends toward an upper surface of the substrate and pass through the pair of heterojunction source/drain regions, respectively.

公开(公告)号：US20180145684A1

公开(公告)日：2018-05-24

申请号：US15654792

申请日：2017-07-20

申请人： Electronics and Telecommunications Research Institute

发明人： Woojin CHANG ,  Jong-Won LIM ,  Dong Min KANG ,  Dong-Young KIM ,  Seong-il KIM ,  Hae Cheon KIM ,  Jae Won DO ,  BYOUNG-GUE MIN ,  Min Jeong SHIN ,  Hokyun AHN ,  Hyung Sup YOON ,  Sang-Heung LEE ,  JONGMIN LEE ,  Sungjae CHANG ,  Yoo Jin JANG ,  HYUNWOOK JUNG ,  Kyu Jun CHO ,  Hong Gu JI

IPC分类号： H03K17/687 ,  H03K17/693 ,  G11C5/14 ,  H03K19/0175 ,  H03K3/353

CPC分类号： H03K17/687 ,  G11C5/14 ,  H03K3/353 ,  H03K17/08122 ,  H03K17/102 ,  H03K17/122 ,  H03K17/145 ,  H03K17/162 ,  H03K17/28 ,  H03K17/693 ,  H03K19/0175

摘要： Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.