公开(公告)号：US11728212B2

公开(公告)日：2023-08-15

申请号：US17211455

申请日：2021-03-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Te-Chih Hsiung ,  Jyun-De Wu ,  Peng Wang ,  Huan-Just Lin

IPC分类号： H01L21/768 ,  H01L21/48 ,  H01L29/78 ,  H01L29/417 ,  H01L23/522

CPC分类号： H01L21/76831 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5221 ,  H01L29/41791 ,  H01L29/785

摘要： A method includes depositing a dielectric cap over a gate structure. A source/drain contact is formed over a source/drain region after forming the dielectric cap. A top of the dielectric cap is doped to form a doped region in the dielectric cap. After doping the top of the dielectric cap, a etch stop layer and an interlayer dielectric (ILD) layer are deposited over the dielectric cap. A via opening is formed to extend though the ILD layer and the etch stop layer to expose the source/drain contact. A source/drain via is filled in the via opening.

公开(公告)号：US09843106B2

公开(公告)日：2017-12-12

申请号：US14510796

申请日：2014-10-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chuei-Tang Wang ,  Jeng-Shieh Hsieh ,  Chung-Hao Tsai ,  Monsen Liu ,  Chen-Hua Yu

IPC分类号： H01Q21/00 ,  H01Q21/06 ,  H01Q1/22 ,  H01Q19/00 ,  H01Q19/10 ,  H01Q19/185

CPC分类号： H01Q21/065 ,  H01L23/66 ,  H01L24/20 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01Q1/2283 ,  H01Q19/005 ,  H01Q19/10 ,  H01Q19/185

摘要： An integrated fan out (InFO) antenna includes a reflector on a surface of a substrate; and a package. The package includes a redistribution layer (RDL) arranged to form an antenna ground, and a patch antenna over the RDL, wherein the RDL is between the patch antenna and the reflector. The InFO antenna further includes a plurality of connecting elements bonding the package to the reflector. Each connecting element of the plurality of connecting elements is located inside an outer perimeter of the reflector. The InFO antenna is configured to output a signal having a wavelength.

公开(公告)号：US09686852B2

公开(公告)日：2017-06-20

申请号：US14680822

申请日：2015-04-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Mark Semmelmeyer ,  Sandeep Kumar Goel

IPC分类号： H05K1/02 ,  H01L25/065 ,  H01L25/00 ,  H05K1/11 ,  H05K1/14 ,  H05K3/46 ,  H01L23/31 ,  H01L21/56 ,  H01L21/66 ,  H01L23/00 ,  H01L23/538

CPC分类号： H05K1/0201 ,  H01L21/561 ,  H01L22/22 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H05K1/11 ,  H05K1/144 ,  H05K3/46 ,  H05K2201/10734 ,  Y10T29/49124 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

摘要： An embodiment is method comprising attaching a first die and a second die to a first surface of a first interposer using respective ones of first conductive connectors coupled to respective first surfaces of the first die and the second die; attaching a third die and a fourth die to a second surface of the first interposer using respective ones of second conductive connectors, the second surface of the first interposer being opposite the first surface of the interposer; and attaching the first die and the second die to a substrate using respective ones of third conductive connectors coupled to respective second surfaces of the first die and the second die.

公开(公告)号：US09224736B1

公开(公告)日：2015-12-29

申请号：US14317907

申请日：2014-06-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ka-Hing Fung ,  Zhiqiang Wu ,  Carlos H. Diaz

IPC分类号： H01L27/00 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/324 ,  H01L27/11 ,  H01L21/8238

CPC分类号： H01L29/7849 ,  H01L21/02161 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

摘要： The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer disposed over the silicon layer and a germanium (Ge) feature disposed over the SiGeO layer. The device also includes a second fin structure over the substrate in a p-type FinFET (PFET) region. The second fin structure includes the silicon (Si) layer, a recessed silicon germanium oxide (SiGeO) layer disposed over the silicon layer, an epitaxial silicon germanium (SiGe) layer disposed over the recessed SiGeO layer and the germanium (Ge) feature disposed over the epitaxial SiGe layer.

摘要翻译： 本公开提供了鳍状场效应晶体管（FinFET）器件的实施例。 该器件包括设置在衬底的n型FinFET（NFET）区域上的第一鳍结构。 第一鳍结构包括硅（Si）层，设置在硅层上的硅锗氧化物（SiGeO）层和设置在SiGeO层上的锗（Ge）特征。 器件还包括在p型FinFET（PFET）区域中的衬底上的第二鳍结构。 第二鳍结构包括硅（Si）层，设置在硅层上的凹陷硅锗氧化物（SiGeO）层，设置在凹陷SiGeO层上的外延硅锗（SiGe）层和设置在其上的锗（Ge）特征 外延SiGe层。

公开(公告)号：US07663916B2

公开(公告)日：2010-02-16

申请号：US11787291

申请日：2007-04-16

申请人： Yue-Der Chih ,  Te-Hsun Hsu

发明人： Yue-Der Chih ,  Te-Hsun Hsu

IPC分类号： G11C11/34

CPC分类号： G11C16/3427 ,  G11C16/0433 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

摘要： An array of memory cells arranged in a plurality of rows and a plurality of columns are provided. The array includes a first program line in a first direction, wherein the first program line is connected to program gates of memory cells in a first row of the array; a first erase line in the first direction, wherein the first erase line is connected to erase gates of the memory cells in the first row of the array; and a first word-line in the first direction, wherein the first word-line is connected to word-line nodes of the memory cells in the first row of the array.

摘要翻译： 提供了布置成多行和多列的存储单元的阵列。 阵列包括第一方向上的第一编程线，其中第一编程线连接到阵列的第一行中的存储器单元的编程门; 在第一方向上的第一擦除线，其中第一擦除线连接到阵列的第一行中的存储器单元的擦除栅极; 以及第一方向上的第一字线，其中第一字线连接到阵列的第一行中的存储器单元的字线节点。

公开(公告)号：US08609308B1

公开(公告)日：2013-12-17

申请号：US13484434

申请日：2012-05-31

申请人： Pei-Shiang Chen ,  Hung-Chun Wang ,  Jeng-Horng Chen ,  Cheng-Hung Chen ,  Shih-Chi Wang ,  Nian-Fuh Cheng ,  Chia-Chi Lin

发明人： Pei-Shiang Chen ,  Hung-Chun Wang ,  Jeng-Horng Chen ,  Cheng-Hung Chen ,  Shih-Chi Wang ,  Nian-Fuh Cheng ,  Chia-Chi Lin

IPC分类号： G03F9/00 ,  G03C5/00

CPC分类号： G06F17/5068 ,  G03F7/20 ,  H01J37/3174 ,  H01J2237/31764 ,  H01J2237/31769 ,  Y10S430/143

摘要： The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.

公开(公告)号：US07688616B2

公开(公告)日：2010-03-30

申请号：US11764618

申请日：2007-06-18

申请人： Yu-Jen Wang ,  Hsu-Chen Chang ,  Denny Tang

发明人： Yu-Jen Wang ,  Hsu-Chen Chang ,  Denny Tang

IPC分类号： G11C11/00

CPC分类号： G11C11/1693 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675

摘要： Thus, the present disclosure provides a method of programming a memory array. At least one memory cell including a magnetic element is provided. At least one current source coupled to the magnetic element is provided. A unipolar current is supplied from the at least one current source to the magnetic element at a plurality of non-zero current levels.

摘要翻译： 因此，本公开提供了一种对存储器阵列进行编程的方法。 提供包括磁性元件的至少一个存储单元。 提供耦合到磁性元件的至少一个电流源。 单极电流从多个非零电流电平从至少一个电流源提供给磁性元件。

公开(公告)号：US10163802B2

公开(公告)日：2018-12-25

申请号：US15583690

申请日：2017-05-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yan-Fu Lin ,  Chen-Hua Yu ,  Meng-Tsan Lee ,  Wei-Cheng Wu ,  Hsien-Wei Chen

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/528 ,  H01L25/10

摘要： A method of forming a package and a package are provided. The method includes placing a main die and a dummy die side by side on a carrier substrate. The method also includes forming a molding material along sidewalls of the main die and the dummy die. The method also includes forming a redistribution layer comprising a plurality of vias and conductive lines over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die. The method also includes removing the carrier substrate.

公开(公告)号：US09449841B2

公开(公告)日：2016-09-20

申请号：US14134914

申请日：2013-12-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shich-Chang Suen ,  Chi-Jen Liu ,  Ying-Liang Chuang ,  Li-Chieh Wu ,  Liang-Guang Chen ,  Ming-Liang Yen

IPC分类号： H01L21/02 ,  H01L21/321 ,  H01L29/66 ,  H01L21/67

CPC分类号： H01L21/28123 ,  B24B37/20 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/67051 ,  H01L29/66545

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor structure including a metal gate (MG) layer formed to fill in a trench between two adjacent interlayer dielectric (ILD) regions; performing a chemical mechanical polishing (CMP) process using a CMP system to planarize the MG layer and the ILD regions; and cleaning the planarized MG layer using a O3/DIW solution including ozone gas (O3) dissolved in deionized water (DIW). The MG layer is formed on the ILD regions.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括提供包括形成为填充两个相邻层间电介质（ILD）区域之间的沟槽的金属栅极（MG）层的半导体结构; 使用CMP系统进行化学机械抛光（CMP）处理以使MG层和ILD区域平坦化; 以及使用溶解在去离子水（DIW）中的包含臭氧气体（O 3）的O 3 / DIW溶液清洗平坦化的MG层。 MG层形成在ILD区域上。

公开(公告)号：US20130141962A1

公开(公告)日：2013-06-06

申请号：US13312810

申请日：2011-12-06

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： G11C11/40

CPC分类号： G11C11/419 ,  G11C11/412 ,  G11C11/413 ,  H01L27/0207 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

摘要： Methods and apparatus for providing single finFET and multiple finFET SRAM arrays on a single integrated circuit. A first single port SRAM array of a plurality of first bit cells is described, each first bit cell having a y pitch Y1 and an X pitch X1, the ratio of X1 to Y1 being greater than or equal to 2, each bit cell further having single fin finFET transistors to form a 6T SRAM cell and a first voltage control circuit; and a second single port SRAM array of a plurality of second bit cells, each second bit cell having a y pitch Y2 and an X pitch X2, the ratio of X2 to Y2 being greater than or equal to 3, each of the plurality of second bit cells comprising a 6T SRAM cell wherein the ratio of X2 to X1 is greater than about 1.1.

摘要翻译： 在单个集成电路上提供单个finFET和多个finFET SRAM阵列的方法和装置。 描述了多个第一位单元的第一单端口SRAM阵列，每个第一位单元具有ay间距Y1和X间距X1，X1与Y1之比大于或等于2，每个位单元还具有单个 鳍式finFET晶体管，形成6T SRAM单元和第一电压控制电路; 以及多个第二位单元的第二单端口SRAM阵列，每个第二位单元具有ay间距Y2和X间距X2，X2与Y2之比大于或等于3，所述多个第二位中的每一个 包含6T SRAM单元的单元，其中X2与X1之比大于约1.1。