公开(公告)号：US09368388B2

公开(公告)日：2016-06-14

申请号：US13446199

申请日：2012-04-13

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L27/11 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

CPC分类号： H01L27/0924 ,  H01L21/76232 ,  H01L21/823431 ,  H01L27/1104 ,  H01L29/66818 ,  H01L29/7853

摘要： A FinFET comprises an isolation region formed in a substrate, a reverse T-shaped fin formed in the substrate, wherein a bottom portion of the reverse T-shaped fin is enclosed by the isolation region and an upper portion of the reverse T-shaped fin protrudes above a top surface of the isolation region. The FinFET further comprises a gate electrode wrapping the reverse T-shaped fin.

公开(公告)号：US08750011B2

公开(公告)日：2014-06-10

申请号：US13423968

申请日：2012-03-19

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： G11C5/06

CPC分类号： G11C17/12 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11226 ,  H01L27/1211

摘要： A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a first second-level contact formed on the first first-level contact, wherein the first second-level contact shifts in a first direction with reference to the first first-level contact. The ROM cell further comprises a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is aligned with the first first-level contact and a second second-level formed on the second first-level contact, wherein the second second-level contact shifts in a second direction with reference to the second first-level contact, and wherein the first direction is opposite to the second direction.

摘要翻译： ROM单元包括形成在存储单元的晶体管的第一有源区上的第一第一电平触点，形成在第一第一级触点上的第一二级触点，其中第一二级触点以第一 方向参考第一级联系人。 ROM单元还包括形成在存储器单元的晶体管的第二有源区上的第二第一电平触点，其中第二第一电平触点与第一第一电平触点对准，第二二级触点形成在第二电平触点上 第二第一级触点，其中所述第二二级触头相对于所述第二第一级触点沿第二方向移动，并且其中所述第一方向与所述第二方向相反。

公开(公告)号：US08625334B2

公开(公告)日：2014-01-07

申请号：US13328685

申请日：2011-12-16

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  H01L27/1104

摘要： A memory cell and array and a method of forming a memory cell and array are described. A memory cell includes first and second pull-up transistors, first and second pull-down transistors, first and second pass-gate transistors, and first and second isolation transistors. Drains of the first pull-up and first pull-down transistors are electrically coupled together at a first node. Drains of the second pull-up and second pull-down transistors are electrically coupled together at a second node. Gates of the second pull-up and second pull-down transistors are electrically coupled to the first node, and gates of the first pull-up and first pull-down transistors are electrically coupled to the second node. The first and second pass-gate transistors are electrically coupled to the first and second nodes, respectively. The first and second isolation transistors are electrically coupled to the first and second nodes, respectively.

公开(公告)号：US20130270652A1

公开(公告)日：2013-10-17

申请号：US13446199

申请日：2012-04-13

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/088

CPC分类号： H01L27/0924 ,  H01L21/76232 ,  H01L21/823431 ,  H01L27/1104 ,  H01L29/66818 ,  H01L29/7853

摘要： A FinFET comprises an isolation region formed in a substrate, a reverse T-shaped fin formed in the substrate, wherein a bottom portion of the reverse T-shaped fin is enclosed by the isolation region and an upper portion of the reverse T-shaped fin protrudes above a top surface of the isolation region. The FinFET further comprises a gate electrode wrapping the reverse T-shaped fin.

摘要翻译： FinFET包括形成在衬底中的隔离区域，形成在衬底中的反向T形翅片，其中反向T形翅片的底部被隔离区域包围，并且反向T形翅片的上部 突出在隔离区域的顶表面上方。 FinFET还包括一个包围反向T形翅片的栅电极。

公开(公告)号：US08409964B2

公开(公告)日：2013-04-02

申请号：US13399488

申请日：2012-02-17

申请人： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

发明人： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

IPC分类号： H01L21/76

CPC分类号： H01L21/823878 ,  H01L21/76232

摘要： A shallow trench isolation (STI) structure and methods of forming a STI structure are disclosed. An embodiment is a method for forming a semiconductor structure. The method includes forming a recess in a semiconductor substrate; forming a first material on sidewalls of the recess; forming a widened recessed portion through a bottom surface of the recess; removing the first material from the sidewalls of the recess; and forming a dielectric material in the recess and the widened recessed portion. The bottom surface of the recess is exposed through the first material, and the bottom surface of the recess has a first width. The widened recessed portion has a second width. The second width is greater than the first width.

摘要翻译： 公开了浅沟槽隔离（STI）结构和形成STI结构的方法。 实施例是形成半导体结构的方法。 该方法包括在半导体衬底中形成凹陷; 在所述凹部的侧壁上形成第一材料; 通过所述凹部的底面形成加宽的凹部; 从所述凹部的侧壁去除所述第一材料; 以及在所述凹部和所述加宽的凹部中形成介电材料。 凹部的底面通过第一材料露出，凹部的底面具有第一宽度。 加宽的凹部具有第二宽度。 第二宽度大于第一宽度。

公开(公告)号：US20120319212A1

公开(公告)日：2012-12-20

申请号：US13598093

申请日：2012-08-29

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/088

CPC分类号： H01L27/11 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/41791 ,  H01L29/785

摘要： A static random access memory (SRAM) cell includes a straight fin and a bended fin physically disconnected from the straight fin. The bended fin has a first portion and a second portion parallel to the straight fin. The distance between the first portion of the bended fin and the straight fin is smaller than the distance between the second portion of the bended fin and the straight fin. The SRAM cell includes a pull-down transistor including a portion of a first gate strip, which forms a first and a second sub pull-down transistor with the straight fin and the first portion of the bended fin, respectively. The SRAM cell further includes a pass-gate transistor including a portion of a second gate strip, which forms a first sub pass-gate transistor with the straight fin. The pull-down transistor includes more fins than the pass-gate transistor.

摘要翻译： 静态随机存取存储器（SRAM）单元包括与直翅片物理断开的直翅片和弯曲的翅片。 弯曲的翅片具有平行于直翅片的第一部分和第二部分。 弯曲翅片的第一部分和直翅片之间的距离小于弯曲翅片的第二部分和直翅片之间的距离。 SRAM单元包括下拉晶体管，其包括第一栅极条的一部分，其分别与直鳍和弯曲鳍的第一部分形成第一和第二子下拉晶体管。 SRAM单元还包括一个包括第二栅极条的一部分的通过栅极晶体管，其形成具有直的鳍的第一子栅极晶体管。 下拉晶体管包括比传输栅极晶体管更多的鳍片。

公开(公告)号：US08120094B2

公开(公告)日：2012-02-21

申请号：US11838666

申请日：2007-08-14

申请人： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

发明人： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119 ,  H01L31/113

CPC分类号： H01L21/823878 ,  H01L21/76232

摘要： A shallow trench isolation (STI) structure has a top portion tapering in width from wide to narrow in a direction from a substrate surface, from a first width at a top of the first portion to a second width at a bottom of the first portion. The STI structure also includes a bottom portion below the top portion, which expands from the bottom of the top portion to a substantially widened lateral distance having a third width. The third width is, in general, substantially larger than the second width. The inventive STI structure can provide desired isolation characteristics with a significantly reduced aspect ratio, thus suitable for device isolations in advanced processing technology.

摘要翻译： 浅沟槽隔离（STI）结构具有在从基板表面的方向上从宽到窄的宽度从第一部分的顶部处的第一宽度到第一部分的底部处的第二宽度的顶部部分。 STI结构还包括在顶部下方的底部，其从顶部的底部膨胀到具有第三宽度的基本上加宽的横向距离。 通常，第三宽度基本上大于第二宽度。 本发明的STI结构可以提供期望的隔离特性，具有显着减小的纵横比，因此适用于先进加工技术中的器件隔离。

公开(公告)号：US20110133285A1

公开(公告)日：2011-06-09

申请号：US12890132

申请日：2010-09-24

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/11

CPC分类号： H01L27/11 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/41791 ,  H01L29/785

摘要： A static random access memory (SRAM) cell includes a straight fin and a bended fin physically disconnected from the straight fin. The bended fin has a first portion and a second portion parallel to the straight fin. The distance between the first portion of the bended fin and the straight fin is smaller than the distance between the second portion of the bended fin and the straight fin. The SRAM cell includes a pull-down transistor including a portion of a first gate strip, which forms a first and a second sub pull-down transistor with the straight fin and the first portion of the bended fin, respectively. The SRAM cell further includes a pass-gate transistor including a portion of a second gate strip, which forms a first sub pass-gate transistor with the straight fin. The pull-down transistor includes more fins than the pass-gate transistor.

摘要翻译： 静态随机存取存储器（SRAM）单元包括与直翅片物理断开的直翅片和弯曲的翅片。 弯曲的翅片具有平行于直翅片的第一部分和第二部分。 弯曲翅片的第一部分和直翅片之间的距离小于弯曲翅片的第二部分和直翅片之间的距离。 SRAM单元包括下拉晶体管，其包括第一栅极条的一部分，其分别与直鳍和弯曲鳍的第一部分形成第一和第二子下拉晶体管。 SRAM单元还包括一个包括第二栅极条的一部分的通过栅极晶体管，其形成具有直的鳍的第一子栅极晶体管。 下拉晶体管包括比传输栅极晶体管更多的鳍片。

公开(公告)号：US20110068413A1

公开(公告)日：2011-03-24

申请号：US12829084

申请日：2010-07-01

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/088 ,  H01L21/8239

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1104

摘要： Circuits and methods for providing a dual gate oxide (DGO) embedded SRAM with additional logic portions, where the logic and the embedded SRAM have NMOS transistors having a common gate dielectric thickness but have different lightly doped drain (LDD) implantations formed using different LDD masks to provide optimum transistor operation. In an embodiment, a first embedded SRAM is a single port device and a second embedded SRAM is a dual port device having a separate read port. In certain embodiments, the second SRAM includes NMOS transistors having LDD implants formed using the logic portion LDD mask. Transistors formed with the logic portion LDD mask are faster and have lower Vt than transistors formed using a SRAM LDD mask. Dual core devices having multiple embedded SRAM arrays are disclosed. Methods for making the embedded SRAM are also disclosed.

摘要翻译： 用于提供具有附加逻辑部分的双栅极氧化物（DGO）嵌入式SRAM的电路和方法，其中逻辑和嵌入式SRAM具有NMOS晶体管，其具有共同的栅极电介质厚度，但具有不同的LDD掩模形成的轻掺杂漏极（LDD）注入 以提供最佳的晶体管操作。 在一个实施例中，第一嵌入式SRAM是单端口设备，第二嵌入式SRAM是具有单独读取端口的双端口设备。 在某些实施例中，第二SRAM包括具有使用逻辑部分LDD掩模形成的LDD注入的NMOS晶体管。 与逻辑部分LDD掩模形成的晶体管比使用SRAM LDD掩模形成的晶体管更快，具有更低的Vt。 公开了具有多个嵌入式SRAM阵列的双核心器件。 还公开了制造嵌入式SRAM的方法。

公开(公告)号：US07906389B2

公开(公告)日：2011-03-15

申请号：US12510951

申请日：2009-07-28

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L21/00

CPC分类号： H01L29/41766 ,  H01L21/28531 ,  H01L21/743 ,  H01L21/7624 ,  H01L21/76802 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

摘要： A butted contact structure forming a source contact electrically connecting a voltage node and a well region and method for forming the same, the butted contact structure including an active region having a well region disposed adjacent an electrical isolation region on a semiconductor substrate; a MOSFET device including a source and drain region on the active region; and, a conductive contact having a first portion formed to the source region and a second portion formed through the electrical isolation region to the doped well region.

摘要翻译： 形成电连接电压节点和阱区的源极接触的对接接触结构及其形成方法，所述对接触点结构包括具有邻近半导体衬底上的电隔离区设置的阱区的有源区; MOSFET器件，其在有源区域上包括源区和漏区; 以及具有形成于所述源极区的第一部分和通过所述电隔离区形成到所述掺杂阱区的第二部分的导电接触。