公开(公告)号：US09093314B2

公开(公告)日：2015-07-28

申请号：US14579326

申请日：2014-12-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jing-Cheng Lin ,  Ya-Hsi Hwung ,  Hsin-Yu Chen ,  Po-Hao Tsai ,  Yan-Fu Lin ,  Cheng-Lin Huang ,  Fang Wen Tsai ,  Wen-Chih Chiou

IPC: H01L21/4763 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L23/488 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05099 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13578 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1369 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer.

Abstract translation: 工件包括具有顶表面和侧壁的铜凸块。 在铜凸块的侧壁而不是顶表面上形成保护层。 保护层包括铜和聚合物的化合物，并且是介电层。

公开(公告)号：US11094641B2

公开(公告)日：2021-08-17

申请号：US16705308

申请日：2019-12-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yan-Fu Lin ,  Chen-Hua Yu ,  Meng-Tsan Lee ,  Wei-Cheng Wu ,  Hsien-Wei Chen

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/528 ,  H01L25/10 ,  H01L23/31 ,  H01L21/48

Abstract: A Fan-Out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.

公开(公告)号：US10510674B2

公开(公告)日：2019-12-17

申请号：US16227725

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yan-Fu Lin ,  Chen-Hua Yu ,  Meng-Tsan Lee ,  Wei-Cheng Wu ,  Hsien-Wei Chen

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/528 ,  H01L25/10 ,  H01L23/31 ,  H01L21/48

Abstract: A method of forming a package and a package are provided. The method includes placing a main die and a dummy die side by side on a carrier substrate. The method also includes forming a molding material along sidewalls of the main die and the dummy die. The method also includes forming a redistribution layer comprising a plurality of vias and conductive lines over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die. The method also includes removing the carrier substrate.

公开(公告)号：US20180151502A1

公开(公告)日：2018-05-31

申请号：US15583690

申请日：2017-05-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yan-Fu Lin ,  Chen-Hua Yu ,  Meng-Tsan Lee ,  Wei-Cheng Wu ,  Hsien-Wei Chen

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/528 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13024 ,  H01L2224/17181 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/73101 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: A method of forming a package and a package are provided. The method includes placing a main die and a dummy die side by side on a carrier substrate. The method also includes forming a molding material along sidewalls of the main die and the dummy die. The method also includes forming a redistribution layer comprising a plurality of vias and conductive lines over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die. The method also includes removing the carrier substrate.

公开(公告)号：US10163802B2

公开(公告)日：2018-12-25

申请号：US15583690

申请日：2017-05-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yan-Fu Lin ,  Chen-Hua Yu ,  Meng-Tsan Lee ,  Wei-Cheng Wu ,  Hsien-Wei Chen

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/528 ,  H01L25/10

Abstract: A method of forming a package and a package are provided. The method includes placing a main die and a dummy die side by side on a carrier substrate. The method also includes forming a molding material along sidewalls of the main die and the dummy die. The method also includes forming a redistribution layer comprising a plurality of vias and conductive lines over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die. The method also includes removing the carrier substrate.

公开(公告)号：US20150111342A1

公开(公告)日：2015-04-23

申请号：US14579326

申请日：2014-12-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jing-Cheng Lin ,  Ya-Hsi Hwung ,  Hsin-Yu Chen ,  Po-Hao Tsai ,  Yan-Fu Lin ,  Cheng-Lin Huang ,  Fang Wen Tsai ,  Wen-Chih Chiou

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/488 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05099 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13578 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1369 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection

Abstract translation: 工件包括具有顶表面和侧壁的铜凸块。 在铜凸块的侧壁而不是顶表面上形成保护层。 保护

公开(公告)号：US20190148305A1

公开(公告)日：2019-05-16

申请号：US16227725

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yan-Fu Lin ,  Chen-Hua Yu ,  Meng-Tsan Lee ,  Wei-Cheng Wu ,  Hsien-Wei Chen

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L23/528

Abstract: A method of forming a package and a package are provided. The method includes placing a main die and a dummy die side by side on a carrier substrate. The method also includes forming a molding material along sidewalls of the main die and the dummy die. The method also includes forming a redistribution layer comprising a plurality of vias and conductive lines over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die. The method also includes removing the carrier substrate.

公开(公告)号：US09852957B2

公开(公告)日：2017-12-26

申请号：US15167256

申请日：2016-05-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Hsien Huang ,  Yung-Shou Cheng ,  Yan-Fu Lin ,  An-Jhih Su ,  Wei-Cheng Wu ,  Chin-Hsien Chen ,  Hsien-Wei Chen ,  Der-Chyang Yeh

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L22/14 ,  H01L21/4846 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/78 ,  H01L22/20 ,  H01L22/32 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2224/83

Abstract: Methods of testing, manufacturing, and packaging semiconductor devices are disclosed. In some embodiments, a method of testing a semiconductor device includes providing an integrated circuit die having contacts disposed thereon, forming an insulating material over the integrated circuit die and the contacts, and forming an opening in the insulating material over the contacts. A eutectic material is formed in the openings over the contacts, and the integrated circuit die is electrically tested by contacting the eutectic material disposed over the contacts. The eutectic material is removed.

公开(公告)号：US20170345726A1

公开(公告)日：2017-11-30

申请号：US15167256

申请日：2016-05-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Hsien Huang ,  Yung-Shou Cheng ,  Yan-Fu Lin ,  An-Jhih Su ,  Wei-Cheng Wu ,  Chin-Hsien Chen ,  Hsien-Wei Chen ,  Der-Chyang Yeh

IPC: H01L21/66 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L22/14 ,  H01L21/4846 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/78 ,  H01L22/20 ,  H01L22/32 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2224/83

Abstract: Methods of testing, manufacturing, and packaging semiconductor devices are disclosed. In some embodiments, a method of testing a semiconductor device includes providing an integrated circuit die having contacts disposed thereon, forming an insulating material over the integrated circuit die and the contacts, and forming an opening in the insulating material over the contacts. A eutectic material is formed in the openings over the contacts, and the integrated circuit die is electrically tested by contacting the eutectic material disposed over the contacts. The eutectic material is removed.