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公开(公告)号:US12119327B2
公开(公告)日:2024-10-15
申请号:US17630870
申请日:2019-07-30
申请人: FUJI CORPORATION
发明人: Ryojiro Tominaga
IPC分类号: B33Y80/00 , H01L25/065 , H05K3/10 , H05K3/46
CPC分类号: H01L25/0657 , H05K3/10 , H05K3/46 , B33Y80/00
摘要: A method for manufacturing a stack component in which an interposer is interposed to form a space for inserting an interlayer connection pin between circuit layers to be stacked, the method includes a printing step of simultaneously printing and forming the circuit layer and the interposer side by side in a planar manner by a 3D printer, a step of mounting a circuit element on the circuit layer, a step of mounting the interposer on the circuit layer, a step of inserting the interlayer connection pin into the interposer mounted on the circuit layer, and a step of electrically connecting the circuit layer and another circuit layer by the interlayer connection pin by stacking the other circuit layer on the circuit layer via the interposer.
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公开(公告)号:US20240215173A1
公开(公告)日:2024-06-27
申请号:US18595910
申请日:2024-03-05
申请人: CelLink Corporation
发明人: Jean-Paul Ortiz , Malcolm Parker Brown , Casey Anderson , Will Findlay , Gabrielle Tate , Shawn D'Gama , Arturo Cantu-Chavez
CPC分类号: H05K3/46 , H05K1/0201 , H05K1/118 , H05K2201/10037
摘要: Provided are flexible interconnect circuits comprising signal circuit elements. For example, a signal circuit element can be formed from the same metal sheet as a signal trace, thereby being monolithic with the signal circuit element. This integration of signal circuit elements into a flexible interconnect circuit reduces the number of additional operations and components (e.g., attaching external circuit elements). In some examples, a flexible interconnect circuit is used in a battery pack for interconnecting batteries while providing external terminals on the same side of the pack. Specifically, a flexible interconnect circuit comprises an interconnecting conductive layer (for connecting to batteries) and a return conductive layer, both extending between the first and second circuit edges. Each of these conductive layers comprises a corresponding external terminal at the first edge, while these layers are interconnected at the second edge. Otherwise, these layers are isolated from each other between the circuit edges.
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公开(公告)号:US20240188209A1
公开(公告)日:2024-06-06
申请号:US18553631
申请日:2022-03-14
申请人: JABIL INC.
CPC分类号: H05K1/0237 , H01P3/08 , H05K3/46
摘要: A printed circuit board (PCB), such as an antenna backplane, including a first conductor and a second conductor forming a differential pair, a first junction and a second junction connected to the first conductor and the second conductor, respectively, and a first impedance matching stub and a second impedance matching stub connected to the first conductor and the second conductor, respectively. The differential pair has a first impedance, the first junction and the second junction have a second impedance, and the first impedance matching stub and the second impedance matching stub match the second impedance to the first impedance. The PCB may have a connector that has differential pins joined to the first and second junctions, and the first impedance matching stub and the second impedance matching stub match an impedance of the junctions, pins, and a connector to the first impedance.
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公开(公告)号:US20230405974A1
公开(公告)日:2023-12-21
申请号:US18229921
申请日:2023-08-03
申请人: CORNING INCORPORATED
发明人: Theresa Chang , Polly Wanda Chu , Patrick Joseph Cimo , Adam James Ellison , Timothy Michael Gross , Guangli Hu , Nicholas James Smith , Butchi Reddy Vaddi , Natesan Venkataraman
IPC分类号: B32B17/10 , C03C21/00 , H05K1/02 , H05K1/03 , C03C17/32 , B32B27/36 , C03C17/30 , C03C15/00 , G06F1/16 , B32B17/06 , C03C3/091 , B32B7/12 , B32B37/12 , B32B37/16 , H05K3/46
CPC分类号: B32B17/10 , G02F1/133305 , H05K1/028 , H05K1/0306 , C03C17/32 , B32B27/36 , C03C17/30 , B32B17/10009 , B32B17/101 , C03C15/00 , B32B17/10137 , G06F1/1652 , B32B17/06 , C03C3/091 , B32B7/12 , B32B37/12 , B32B37/16 , H05K3/46 , Y10T428/24942 , Y10T428/26 , Y10T428/266 , C03C21/002
摘要: A glass element having a thickness from 25 μm to 125 μm, a first primary surface, a second primary surface, and a compressive stress region extending from the first primary surface to a first depth, the region defined by a compressive stress σI of at least about 100 MPa at the first primary surface. Further, the glass element has a stress profile such that it does not fail when it is subject to 200,000 cycles of bending to a target bend radius of from 1 mm to 20 mm, by the parallel plate method. Still further, the glass element has a puncture resistance of greater than about 1.5 kgf when the first primary surface of the glass element is loaded with a tungsten carbide ball having a diameter of 1.5 mm.
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公开(公告)号:US20230387600A1
公开(公告)日:2023-11-30
申请号:US18250815
申请日:2021-10-21
发明人: YOSHITAKA YOSHINO , SATORU TSUBOI
摘要: [Solving Means] A horn antenna according to an embodiment of the present technology includes: a waveguide portion; and a horn portion. The waveguide portion includes a first dielectric block and a first post wall, the first post wall including a plurality of conductive columnar bodies that passes through the first dielectric block and demarcating a first waveguide that extends in one axial direction. The horn portion includes a first widening portion that is connected to one end of the waveguide portion in the one axial direction. The first widening portion includes a second dielectric block that is thicker than the first dielectric block and a second post wall that includes a plurality of conductive columnar bodies and demarcates a second waveguide whose width increases as a distance from the first waveguide increases, the plurality of conductive columnar bodies passing through the second dielectric block.
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公开(公告)号:US20230319976A1
公开(公告)日:2023-10-05
申请号:US18124450
申请日:2023-03-21
CPC分类号: H05K1/0213 , H05K1/144 , H05K3/46 , H05K2201/026 , H05K2201/0379 , H05K2203/02 , H05K2201/058
摘要: A carrier assembly may include a first carrier sub-assembly, said first carrier sub-assembly having an elongated shape and comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure, said at least one electrically conductive layer structure extending up to a first area provided on one of two extremities of the elongated shape, wherein a first plurality of conductive nanowires is provided on said first area, and a second carrier sub-assembly, said second carrier sub-assembly comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure, said at least one electrically conductive layer structure comprising a second area, wherein a second plurality of conductive nanowires is provided on that second area.
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公开(公告)号:US11756846B2
公开(公告)日:2023-09-12
申请号:US15930696
申请日:2020-05-13
发明人: Tetsuyuki Tsuchida
摘要: A glass core, a multilayer circuit board, and a method of manufacturing a glass core that appropriately form copper wiring, and suppresses crack and the like, a glass core includes: a glass plate; a first metal layer provided on the glass plate; a first electrolytic copper plating layer provided on the first metal layer; a dielectric layer provided above the first electrolytic copper plating layer; a second metal layer provided on the dielectric layer; an electroless nickel plating layer provided on the second metal layer and having a phosphorus content of less than 5 mass %; and a second electrolytic copper plating layer provided on the electroless nickel plating layer.
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公开(公告)号:US20230240009A1
公开(公告)日:2023-07-27
申请号:US18127295
申请日:2023-03-28
申请人: TOPPAN INC.
发明人: Takeshi TAKADA , Yuki UMEMURA
CPC分类号: H05K1/09 , H05K3/42 , H05K2201/0137 , H05K2203/072 , H05K3/46
摘要: A wiring board includes a first wiring layer disposed on the first adhesion layer; and a second wiring layer disposed on the second adhesion layer, wherein a proportion of copper remaining in the first wiring layer is represented by C=B/A (%), where A is a total area of the first wiring layer, B is an area of copper in the first wiring layer, and C is a remaining copper ratio C defined as the proportion of copper remaining in the first wiring layer, and wherein when the remaining copper ratio C is set to 70 to 100%, the first adhesion layer is comprised of at least one material having a first predetermined Young's modulus, and the first wiring layer is comprised of at least one material having a second predetermined Young's modulus, the first predetermined Young's modulus being 0.1 to 0.85 times the second predetermined Young's modulus.
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公开(公告)号:US11711897B2
公开(公告)日:2023-07-25
申请号:US17027815
申请日:2020-09-22
发明人: Toshikazu Takagi
CPC分类号: H05K3/429 , H01L23/3675 , H01L23/4006 , H02M7/003 , H05K1/0215 , H05K3/32 , H05K3/46 , H05K7/20436 , H01L2023/4018 , H05K2201/10409
摘要: The power conversion device includes: a main circuit having first and second wiring layers formed respectively on both surfaces of a base board, mounted parts mounted on the first and second wiring layers, and first and second GND layers formed respectively, between external- and internal-layer portions of the base board and in regions corresponding to the mounted parts each being a mounted part which forms a circuit other than a circuit having an inductance component as a lumped constant, and to the first and second wiring layers; and a cooler attached to the base board by means of fixing screws through a first through-hole created in an end portion of the board; wherein the first and second GND layers are each formed so that creepage distance is created around a second through-hole in which a lead insertion part that mutually connects the first and second wiring layers is inserted.
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公开(公告)号:US11665832B2
公开(公告)日:2023-05-30
申请号:US17234805
申请日:2021-04-20
发明人: John Hon-Shing Lau , Cheng-Ta Ko , Pu-Ju Lin , Chi-Hai Kuo , Kai-Ming Yang , Chia-Yu Peng , Shao-Chien Lee , Tzyy-Jang Tseng
IPC分类号: H05K1/00 , H05K1/02 , H05K1/03 , H05K1/09 , H05K1/11 , H05K1/14 , H05K1/16 , H05K1/18 , H05K3/20 , H05K3/36 , H05K3/38 , H05K3/40 , H05K3/46 , H05K3/02
CPC分类号: H05K3/46 , H05K3/022 , H05K3/386 , H05K3/4038
摘要: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.
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