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    MULTILEVEL STORAGE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE ENABLING HIGH-SPEED DATA READING AND HIGH-SPEED DATA WRITING
    81.
    发明申请
    MULTILEVEL STORAGE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE ENABLING HIGH-SPEED DATA READING AND HIGH-SPEED DATA WRITING 有权
    多存储非易失性半导体存储器件启用高速数据读取和高速数据写入

    公开(公告)号：US20100135079A1

    公开(公告)日：2010-06-03

    申请号：US12697852

    申请日：2010-02-01

    Applicant: Yuichi KUNORI

    Inventor： Yuichi KUNORI

    IPC: G11C16/04 ,  G11C7/00

    CPC classification number: G11C11/5621 ,  G11C11/5628 ,  G11C11/5642

    Abstract: A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence to 2n threshold levels. A write data conversion circuit generates write data from bit data input from the same data input/output terminal in a set of a plurality of data of j bits input at different timings.

    Abstract translation: 非易失性半导体存储器件每j位（例如8位）向/从数据输入/输出端子发送/接收数据。 存储单元阵列中的每个存储单元可以对应于2n个阈值电平保存n位的数据。 写入数据转换电路从以不同定时输入的多个j位数据的集合中的同一数据输入/输出端输入的位数据生成写入数据。

    Floor plan evaluating method, floor plan correcting method, program, floor plan evaluating device, and floor plan creating device
    83.
    发明授权
    Floor plan evaluating method, floor plan correcting method, program, floor plan evaluating device, and floor plan creating device 有权
    平面图评估方法，平面图校正方法，程序，平面图评估装置和平面图制作装置

    公开(公告)号：US07730439B2

    公开(公告)日：2010-06-01

    申请号：US11659110

    申请日：2005-05-12

    Applicant: Ken Saito ,  Yoshio Inoue

    Inventor： Ken Saito ,  Yoshio Inoue

    IPC: G06F17/50

    CPC classification number: G06F17/5072

    Abstract: A floor plan evaluation method by which a floor plan can be quantitatively evaluated. The floor plan evaluation method includes first extracting a plurality of specified elements, which are specified in advance from data on a floor plan which is made automatically by, e.g., a floor planner, second obtaining an individual evaluation value on each of a plurality of individual evaluation items on the basis of the plurality of specified elements extracted in the first step, and third calculating an integrated evaluation value on the floor plan on the basis of a plurality of individual evaluation values obtained in the second step. Then, a plurality of integrated evaluation values obtained by executing the first to third operations for a plurality of floor plans are compared with one another to relatively evaluate the plurality of floor plans.

    Abstract translation: 可以对楼层平面图进行定量评价的平面图评价方法。 平面图评估方法包括首先提取多个指定元素，该多个指定元素预先从由例如平面布置者自动制作的平面图上的数据中提取，第二个获得多个个体中的每一个上的个体评估值 基于在第一步骤中提取的多个指定元素的评估项目，并且基于在第二步骤中获得的多个个体评估值，在平面图上计算综合评估值。 然后，将通过执行多个平面图的第一至第三操作而获得的多个综合评估值彼此进行比较，以相对评估多个平面图。

    MULTI-CORE MICROCONTROLLER HAVING COMPARATOR FOR CHECKING PROCESSING RESULT
    84.
    发明申请
    MULTI-CORE MICROCONTROLLER HAVING COMPARATOR FOR CHECKING PROCESSING RESULT 有权
    具有检测加工结果的多核微型计算机

    公开(公告)号：US20100131741A1

    公开(公告)日：2010-05-27

    申请号：US12610422

    申请日：2009-11-02

    Applicant: Hiromichi YAMADA ,  Kotaro Shimamura ,  Kesami Hagiwara ,  Yoshikazu Kiyoshige ,  Yuichi Ishiguro

    Inventor： Hiromichi YAMADA ,  Kotaro Shimamura ,  Kesami Hagiwara ,  Yoshikazu Kiyoshige ,  Yuichi Ishiguro

    IPC: G06F9/30 ,  G06F9/44 ,  G06F9/38

    CPC classification number: G06F11/1608 ,  G06F11/004 ,  G06F11/1641 ,  G06F11/1687 ,  G06F2201/83 ,  G06F2201/845

    Abstract: A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.

    Abstract translation: 一种微控制器，其能够通过由多个CPU执行不同的程序来提高处理性能，并且能够通过评估由多个CPU执行的相同处理的结果来检测用于安全需要的处理的异常。 提供了包括CPU和存储器在内的多个处理系统，每个处理系统中的CPU输出的数据分别由用于每个CPU的压缩机压缩和存储。 压缩存储数据由比较器相互比较，当比较结果表示不匹配时，可以检测出异常处理。 即使当多个CPU异步地执行相同的处理时，获得相同处理结果的定时也是不同的，因此可以容易地将它们的处理结果彼此进行比较，因为压缩是由压缩器执行的。 此外，由于在从所有CPU给出比较使能时能够进行比较器的比较，所以可以基于确定多个压缩机的压缩结果的定时来获得比较运算结果。

    Method for smoothing a resist pattern prior to etching a layer using the resist pattern
    86.
    发明授权
    Method for smoothing a resist pattern prior to etching a layer using the resist pattern 失效
    在使用抗蚀剂图案蚀刻层之前使抗蚀剂图案平坦化的方法

    公开(公告)号：US07723235B2

    公开(公告)日：2010-05-25

    申请号：US11571853

    申请日：2005-06-10

    Applicant: Masaru Kurihara ,  Masaru Izawa

    Inventor： Masaru Kurihara ,  Masaru Izawa

    IPC: H01L21/311 ,  H01L21/3065

    CPC classification number: H01L21/28035 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76885 ,  H01L29/6659 ,  H01L29/7833

    Abstract: After a polycrystalline silicon film (5) is formed on a semiconductor substrate via an insulating film for a gate insulating film (step S1), an organic antireflection film (21) is formed on the polycrystalline silicon film (5) (step S2), and a resist pattern (22) is formed on the antireflection film (21) (step S3). Then, a passivation film (23) is deposited on the antireflection film (21) so as to cover the resist pattern (22) by plasma using fluorocarbon gas while a bias voltage is being applied to the semiconductor substrate (step S4). Then, the passivation film (23) and the antireflection film (21) are etched by plasma using gas containing oxygen gas (step S5). Thereafter, the polycrystalline silicon film (5) is etched using the resist pattern (22) with reduced line edge roughness as an etching mask to form a gate electrode (step S6).

    Abstract translation: 在通过栅极绝缘膜用绝缘膜在半导体基板上形成多晶硅膜（5）（步骤S1）之后，在多晶硅膜（5）上形成有机防反射膜（21）（步骤S2） 并且在防反射膜（21）上形成抗蚀剂图案（22）（步骤S3）。 然后，在防反射膜（21）上沉积钝化膜（23），以便在对半导体衬底施加偏置电压的同时使用碳氟化合物气体通过等离子体覆盖抗蚀剂图案（步骤S4）。 然后，使用含氧气体的等离子体蚀刻钝化膜（23）和防反射膜（21）（步骤S5）。 此后，使用具有减小的线边缘粗糙度的抗蚀剂图案（22）蚀刻多晶硅膜（5）作为蚀刻掩模以形成栅电极（步骤S6）。

    Semiconductor device with surge protection circuit
    87.
    发明授权
    Semiconductor device with surge protection circuit 有权
    具有浪涌保护电路的半导体器件

    公开(公告)号：US07719814B2

    公开(公告)日：2010-05-18

    申请号：US11826090

    申请日：2007-07-12

    Applicant: Mutsuo Kobayashi ,  Tsukasa Ooishi

    Inventor： Mutsuo Kobayashi ,  Tsukasa Ooishi

    IPC: H02H3/22 ,  G11C7/24

    CPC classification number: G11C5/147 ,  G11C16/04 ,  G11C16/30 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/50004 ,  G11C29/52

    Abstract: A semiconductor device includes a memory cell to and from which data is written and read in accordance with voltage supplied, a power supply circuit generating the voltage supplied to the memory cell, a microcomputer, an external terminal, a surge protection circuit clamping at a predetermined voltage value a voltage supplied to the external terminal, and a first switch circuit switching to output to one of the power supply circuit and the microcomputer a voltage having passed through the surge protection circuit. The power supply circuit includes a voltage conversion circuit changing the magnitude of a voltage received from the first switch circuit, and a second switch circuit switching to supply the memory cell with one of the voltage received from the first switch circuit and the voltage changed in magnitude.

    Abstract translation: 一种半导体器件包括一个根据所提供的电压写入和读出数据的存储单元，一个产生提供给存储单元的电压的电源电路，一个微型计算机，一个外部端子，一个预定的钳位电流保护电路 电压值，提供给外部端子的电压，以及第一开关电路，切换为向电源电路和微计算机中的一个输出通过浪涌保护电路的电压。 电源电路包括电压转换电路，其改变从第一开关电路接收的电压的大小，以及第二开关电路，其切换以向存储单元提供从第一开关电路接收的电压中的一个和电压变化的电压 。

    Semiconductor device and method of producing the same
    88.
    发明授权
    Semiconductor device and method of producing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07719078B2

    公开(公告)日：2010-05-18

    申请号：US12265430

    申请日：2008-11-05

    Applicant: Kazuo Tomita

    Inventor： Kazuo Tomita

    IPC: H01L29/00

    CPC classification number: H01L21/76229 ,  H01L21/31053 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.

    Abstract translation: 在具有由沟槽型隔离氧化膜13构成的元件隔离的半导体器件中，作为虚设的有源区的两种类型的大型和小型虚拟图案11位于隔离区域10中，大的虚设图案11b为 布置在远离实际图案9的位置处，并且小实际图案11a被规则地布置在实际图案9的周围的间隙中，从而在研磨隔离氧化膜13a时提高了研磨速度的均匀性 并且半导体器件的表面平坦度变得更好。

    MAGNETIC MEMORY DEVICE
    89.
    发明申请
    MAGNETIC MEMORY DEVICE 失效
    磁记忆装置

    公开(公告)号：US20100118581A1

    公开(公告)日：2010-05-13

    申请号：US12611600

    申请日：2009-11-03

    Applicant: Shota OKAYAMA

    Inventor： Shota OKAYAMA

    IPC: G11C11/02 ,  G11C5/02

    CPC classification number: G11C5/025 ,  G11C11/1653 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673

    Abstract: The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of memory cell forming regions. Contacts relative to the gate word line protrusions are respectively provided at boundary regions of memory cells at adjacent columns. The drain impurity regions are respectively disposed with being shifted from the centers of the memory cell forming regions in such a manner that spaces between the drain impurity regions become large in the regions in which the protrusions are disposed.

    Abstract translation: 本发明提供一种能够在不增加阵列区域的情况下提供高速存取的磁存储装置。 栅极字线分别线性地设置在存储单元阵列区域内的源极杂质区域和漏极杂质区域之间。 栅极字线突起分别设置在存储单元形成区域的边界区域。 在相邻列的存储单元的边界区域分别提供相对于栅极字线突起的触点。 漏极杂质区域分别设置成从存储单元形成区域的中心偏移，使得在布置有突起的区域中，漏极杂质区域之间的空间变大。

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