公开(公告)号：US08598691B2

公开(公告)日：2013-12-03

申请号：US13228757

申请日：2011-09-09

Applicant: Sheng-Yu Wu ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Ming-Da Cheng

Inventor： Sheng-Yu Wu ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Ming-Da Cheng

IPC: H01L23/695 ,  H01L29/40

CPC classification number: H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/13014 ,  H01L2224/13147 ,  H01L2224/141 ,  H01L2224/14136 ,  H01L2224/14145 ,  H01L2224/14156 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Semiconductor devices and methods of manufacturing and packaging thereof are disclosed. In one embodiment, a semiconductor device includes an integrated circuit and a plurality of copper pillars coupled to a surface of the integrated circuit. The plurality of copper pillars has an elongated shape. At least 50% of the plurality of copper pillars is arranged in a substantially centripetal orientation.

Abstract translation: 公开了半导体器件及其制造和封装方法。 在一个实施例中，半导体器件包括集成电路和耦合到集成电路的表面的多个铜柱。 多个铜柱具有细长的形状。 多个铜柱的至少50％被布置成基本上向心的取向。

公开(公告)号：US20130285238A1

公开(公告)日：2013-10-31

申请号：US13460412

申请日：2012-04-30

Applicant: Meng-Tse CHEN ,  Hsiu-Jen LIN ,  Chih-Wei LIN ,  Cheng-Ting CHEN ,  Ming-Da CHENG ,  Chung-Shi LIU

Inventor： Meng-Tse CHEN ,  Hsiu-Jen LIN ,  Chih-Wei LIN ,  Cheng-Ting CHEN ,  Ming-Da CHENG ,  Chung-Shi LIU

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L24/14 ,  H01L21/4853 ,  H01L23/3677 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/1134 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.

Abstract translation: 半导体封装结构包括衬底，与衬底结合的管芯，以及将管芯连接到衬底的一个或多个柱塞凸块结构，其中每个凸起凸块结构具有柱形凸起和封装凸起凸起的焊球，以增强 散热并减少半导体封装结构中的高应力集中。

公开(公告)号：US20130157455A1

公开(公告)日：2013-06-20

申请号：US13765280

申请日：2013-02-12

Applicant: International Buiness Machines Corporation

Inventor： David Justin West ,  David John Russell

IPC: H01L21/02

CPC classification number: H01L21/02697 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/1132 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/16238 ,  H01L2224/17515 ,  H01L2224/17517 ,  H01L2224/81141 ,  H01L2224/81194 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/131 ,  H01L2924/00

Abstract: An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

Abstract translation: 一种电子装置和该装置的制造方法，该装置包括第一电子装置，该第一电子装置具有互连表面，该第一电子装置具有从表面延伸第一距离的第一多个互连焊盘以及从该表面延伸的第二多个对准柱 第二距离大于第一距离;以及第二电气设备，其具有与第一多个电互连焊盘的互连表面，每个焊盘布置成在第一电子设备互连表面组装时接触相应的第一电子设备互连表面焊盘 第二电子设备互连表面，所述第二电子设备互连表面包括第三多个对准柱，每个定位柱在组装时定位成与所述第一电子设备对准柱中的至少一个相邻。

公开(公告)号：US20120292745A1

公开(公告)日：2012-11-22

申请号：US13112172

申请日：2011-05-20

Applicant: YeongIm Park ,  HeeJo Chi ,  HyungMin Lee

Inventor： YeongIm Park ,  HeeJo Chi ,  HyungMin Lee

IPC: H01L25/07 ,  H01L21/98

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/481 ,  H01L23/552 ,  H01L24/14 ,  H01L24/17 ,  H01L24/48 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14136 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/93 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a substrate and plurality of first semiconductor die having conductive vias formed through the first semiconductor die mounted with an active surface oriented toward the substrate. An interconnect structure, such as bumps or conductive pillars, is formed over the substrate between the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The second semiconductor die is electrically connected through the interconnect structure to the substrate and through the conductive vias to the first semiconductor die. An underfill material is deposited between the first semiconductor die and substrate. Discrete electronic components can be mounted to the substrate. A heat spreader or shielding layer is mounted over the first and second semiconductor die and substrate. Alternatively, an encapsulant is formed over the die and substrate and conductive vias or bumps are formed in the encapsulant electrically connected to the first die.

Abstract translation: 半导体器件具有衬底和多个第一半导体管芯，其具有通过第一半导体管芯形成的导电通孔，所述导电通孔安装有朝向衬底的有源表面。 在第一半导体管芯之间的衬底上形成诸如凸起或导电柱的互连结构。 第二半导体管芯安装到第一半导体管芯。 第二半导体管芯通过互连结构电连接到衬底并且通过导电通孔连接到第一半导体管芯。 在第一半导体管芯和衬底之间沉积底部填充材料。 离散电子部件可以安装在基板上。 散热器或屏蔽层安装在第一和第二半导体管芯和衬底上。 或者，在管芯和衬底上形成密封剂，并且在与第一管芯电连接的密封剂中形成导电通孔或凸块。

公开(公告)号：US20120228763A1

公开(公告)日：2012-09-13

申请号：US13398372

申请日：2012-02-16

Applicant: Naoto AKIYAMA ,  Takashi NAKAYAMA ,  Hiroshi KISHIBE ,  Takefumi HIRAGA

Inventor： Naoto AKIYAMA ,  Takashi NAKAYAMA ,  Hiroshi KISHIBE ,  Takefumi HIRAGA

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/5286 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05078 ,  H01L2224/05551 ,  H01L2224/05558 ,  H01L2224/0569 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13028 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/14177 ,  H01L2224/16106 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/01047

Abstract: A semiconductor device including a pillar formed in a highly reliable manner and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a semiconductor chip including an internal circuit area and an I/O area disposed outside the internal circuit area, a package substrate coupled in a flip-chip manner to the semiconductor chip, and an electrically conductive pillar disposed between the semiconductor chip and the package substrate such that the electrically conductive pillar is located over two or more wirings in an uppermost wiring layer of the semiconductor chip and such that the two or more wirings are coupled together via the electrically conductive pillar.

Abstract translation: 公开了一种包括以高度可靠的方式形成的柱的半导体器件和制造该半导体器件的方法。 半导体器件包括：半导体芯片，包括内部电路区域和布置在内部电路区域外部的I / O区域;以半导体芯片的倒装芯片方式耦合的封装基板;以及设置在半导体芯片 以及所述封装基板，使得所述导电柱位于所述半导体芯片的最上布线层中的两条或更多条布线之上，并且使得所述两条或更多条布线经由所述导电柱连接在一起。

公开(公告)号：US07935408B2

公开(公告)日：2011-05-03

申请号：US11924662

申请日：2007-10-26

Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: B32B3/10 ,  B05D5/12 ,  H01L23/485

CPC classification number: H01L21/563 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/14136 ,  H01L2224/26152 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/831 ,  H01L2224/83385 ,  H01L2225/06513 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/19043 ,  Y10S428/901 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/4921 ,  Y10T29/49222 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/24339 ,  Y10T428/24347 ,  Y10T428/24479 ,  Y10T428/24529 ,  Y10T428/24545 ,  Y10T428/24612 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An electrical structure and method of forming. The electrical structure includes a first substrate, first dielectric layer, an underfill layer, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectric layer includes a first opening extending through a top surface and a bottom surface of said first dielectric layer. The underfill layer is formed over the top surface of the first dielectric layer and within the first opening. The second substrate is formed over and in contact with the underfill layer.

Abstract translation: 一种电气结构和成型方法。 电结构包括第一衬底，第一介电层，底部填充层和第二衬底。 第一介电层形成在第一基板的顶表面上。 第一电介质层包括延伸穿过所述第一电介质层的顶表面和底表面的第一开口。 底部填充层形成在第一介电层的顶表面上并且在第一开口内。 第二衬底形成在底部填充层上并与底部填充层接触。

公开(公告)号：US20100022050A1

公开(公告)日：2010-01-28

申请号：US12571234

申请日：2009-09-30

Applicant: TaeWoo Kang ,  YoRim Lee ,  TaeKeun Lee

Inventor： TaeWoo Kang ,  YoRim Lee ,  TaeKeun Lee

IPC: H01L21/60

CPC classification number: H05K3/303 ,  H01L24/11 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/06515 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/14515 ,  H01L2224/16 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/0305 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00

Abstract: A semiconductor device is made by disposing a film layer over a substrate having first conductive layer. An opening is formed in the film layer to expose the first conductive layer. A second conductive layer is formed over the first conductive layer. A first bump is formed over the second conductive layer which promotes reflow of the first bump at a eutectic temperature. A standoff bump is formed on the film layer around a perimeter of the substrate. The film layer prevents reflow of the standoff bump at the eutectic temperature. A second bump is disposed between a semiconductor die and the first bump. The second bump is reflowed to electrically connect the semiconductor die to the first bump. After reflow of the second bump, the standoff bump has a height at least 70% of the second bump prior to reflow to maintain separation between the semiconductor die and substrate.

Abstract translation: 半导体器件通过在具有第一导电层的衬底上设置膜层而制成。 在膜层中形成开口以露出第一导电层。 在第一导电层上形成第二导电层。 在第二导电层上形成第一凸块，其促进在共晶温度下第一凸块的回流。 在基片周边的薄膜层上形成间隙凸点。 膜层防止在共晶温度下的支座凸起的回流。 第二凸块设置在半导体管芯和第一凸块之间。 第二凸块被回流以将半导体管芯电连接到第一凸块。 在第二凸块的回流之后，在回流之前，间隙凸块的高度至少为第二凸块的70％，以保持半导体管芯和衬底之间的间隔。

公开(公告)号：US07164208B2

公开(公告)日：2007-01-16

申请号：US11037262

申请日：2005-01-19

Applicant: Kazuyuki Kainou ,  Masatoshi Yagoh ,  Kimihito Kuwabara ,  Katsumi Ohtani

Inventor： Kazuyuki Kainou ,  Masatoshi Yagoh ,  Kimihito Kuwabara ,  Katsumi Ohtani

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/02122 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/0614 ,  H01L2224/06141 ,  H01L2224/06177 ,  H01L2224/06179 ,  H01L2224/13006 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/1414 ,  H01L2224/14141 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/81805

Abstract: There is provided a semiconductor device in which the junction strength of land portions and external terminals is increased, the disconnection of the external terminal is surely prevented, and the connection reliability is ensured over an extended period of time. An insulating resin layer which insulates metal wires from one another is formed on a semiconductor element, an end portion of the metal wire is connected to an electrode on the semiconductor element, the other end portion of the metal wire is connected to an external terminal to form a land, the entire surface of the semiconductor element except the connecting portions of the lands is covered with a surface-layer resin layer, and a projection is provided on the top surface of a land portion of at least one of the lands. Because of this, after their soldering, the external terminal holds the perimeter of the projection on the land portion, so that the external terminal can be surely connected to the land portion. As a result, the semiconductor device which ensures their connection reliability over an extended period of time can be obtained.

Abstract translation: 提供了一种半导体装置，其中陆部和外部端子的结合强度增加，可靠地防止外部端子的断开，并且在延长的时间段内确保连接可靠性。 在半导体元件上形成绝缘树脂层，金属线彼此连接，金属线的端部与半导体元件上的电极连接，金属线的另一端部与外部端子连接 形成一个焊盘，除了焊盘的连接部分之外的半导体元件的整个表面被表面层树脂层覆盖，并且在至少一个焊盘的焊盘部分的顶表面上设置突起。 因此，在焊接之后，外部端子将突起的周边保持在陆部上，使得外部端子可以可靠地连接到陆部。 结果，可以获得确保其在较长时间段内的连接可靠性的半导体器件。

公开(公告)号：US06491968B1

公开(公告)日：2002-12-10

申请号：US09474789

申请日：1999-12-29

Applicant: Gaetan L. Mathieu ,  Benjamin N. Eldridge ,  Gary W. Grube

Inventor： Gaetan L. Mathieu ,  Benjamin N. Eldridge ,  Gary W. Grube

IPC: B05D512

CPC classification number: G01R3/00 ,  G01R1/06727 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/13011 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14133 ,  H01L2224/14136 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/30105 ,  H05K3/326 ,  H05K3/4092 ,  Y10S156/941 ,  Y10T29/49147 ,  Y10T29/49204 ,  Y10T29/49224 ,  Y10T156/19 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2224/05655

Abstract: A method including fabricating a multi-tiered structure to form a compact, resilient interconnect structure. Fabricating each tier or leaf includes, in one aspect, providing a base substrate material, and applying a masking material over the base substrate material. An opening is patterned in the masking material and a resilient element is formed in the opening. A resilient element is coupled to the resilient element to form the resulting product. The method includes repeating this process one or more times to fabricate a chip-level interconnection element. The interconnection element fabricated, in another aspect, is of a size suitable for contacting a packaged semiconductor device, such as in an LGA package.

Abstract translation: 一种包括制造多层结构以形成紧凑的弹性互连结构的方法。 在一个方面中，制造每个层或叶包括提供基底材料，以及在基底材料上施加掩模材料。 在掩模材料中形成开口，并且在开口中形成弹性元件。 弹性元件联接到弹性元件以形成所得到的产品。 该方法包括重复该过程一次或多次以制造芯片级互连元件。 在另一方面，制造的互连元件的尺寸适合于诸如LGA封装中的封装半导体器件的接触。

公开(公告)号：US20190244925A1

公开(公告)日：2019-08-08

申请号：US16385399

申请日：2019-04-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： KUAN-YU HUANG ,  TZU-KAI LAN ,  SHOU-CHIH YIN ,  SHU-CHIA HSU ,  PAI-YUAN LI ,  SUNG-HUI HUANG ,  HSIANG-FAN LEE ,  YING-SHIN HAN

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L25/18

CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11013 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14505 ,  H01L2224/16111 ,  H01L2224/16112 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device includes an electronic component, a package, a substrate and a plurality of first conductors and second conductors. The package is over the electronic component. T substrate is between the electronic component and the package. The substrate includes a first portion covered by the package, and a second portion protruding out of an edge of the package and uncovered by the package. The first conductors and second conductors are between and electrically connected to the electronic component and the substrate. A width of a second conductor of the plurality of second conductors is larger than a width of a first conductor of the plurality of first conductors, the first conductors are disposed between the second portion of the substrate and the electronic component, and the second conductors are disposed between the first portion of the substrate and the electronic component.