公开(公告)号：US09991190B2

公开(公告)日：2018-06-05

申请号：US13475674

申请日：2012-05-18

Applicant: Hui-Min Huang ,  Yen-Chang Hu ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Chen-Shien Chen

Inventor： Hui-Min Huang ,  Yen-Chang Hu ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Chen-Shien Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/495 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/19 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The mechanisms of using an interposer frame to package a semiconductor die enables fan-out structures and reduces form factor for the packaged semiconductor die. The mechanisms involve using a molding compound to attach the semiconductor die to the interposer frame and forming a redistribution layer on one or both sides of the semiconductor die. The redistribution layer(s) in the package enables fan-out connections and formation of external connection structures. Conductive columns in the interposer frame assist in thermal management.

公开(公告)号：US09786622B2

公开(公告)日：2017-10-10

申请号：US13277575

申请日：2011-10-20

Applicant: Ming-Da Cheng ,  Chih-Wei Lin ,  Kuei-Wei Huang ,  Yu-Peng Tsai ,  Chun-Cheng Lin ,  Chung-Shi Liu

Inventor： Ming-Da Cheng ,  Chih-Wei Lin ,  Kuei-Wei Huang ,  Yu-Peng Tsai ,  Chun-Cheng Lin ,  Chung-Shi Liu

IPC: H01L23/488 ,  H01L23/00

CPC classification number: H01L24/16 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05572 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/1601 ,  H01L2224/16104 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/206 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The distance between the conductive pillar and the conductive trace is less than or equal to about 16 μm.

公开(公告)号：US09543185B2

公开(公告)日：2017-01-10

申请号：US13309311

申请日：2011-12-01

Applicant: Wei-Hung Lin ,  Kuei-Wei Huang ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Wei-Hung Lin ,  Kuei-Wei Huang ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: B23Q3/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/11444 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/14135 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75754 ,  H01L2224/7698 ,  H01L2224/81001 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83102 ,  H01L2224/9205 ,  H01L2224/92125 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/3841 ,  Y10T29/41 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/05552 ,  H01L2924/013

Abstract: Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Abstract translation: 公开了用于半导体器件的封装加工工具和系统以及封装方法。 在一个实施例中，用于半导体器件的封装处理工具包括用于在集成电路管芯的封装工艺期间支撑封装衬底或集成电路管芯的机械结构。 机械结构包括设置在其上的低热导率材料。

公开(公告)号：US20150018484A1

公开(公告)日：2015-01-15

申请号：US14249702

申请日：2014-04-10

Applicant: Chih-Wei Lin ,  Meng-Ying Tsai

Inventor： Chih-Wei Lin ,  Meng-Ying Tsai

IPC: C08J5/18 ,  B29C39/00

CPC classification number: C08J5/18 ,  B29C39/003 ,  B29K2079/08 ,  B29K2105/0032 ,  C08G73/1067 ,  C08G73/1071 ,  C08J2379/08 ,  C09D179/08

Abstract: A polyimide film includes a polyimide polymer forming a main molecular structure of the polyimide film, and polyimide particles present in the polyimide film at a weight ratio between about 15 wt % and 30 wt % of a total weight of the polyimide film, the polyimide particles having an average diameter between about 3 μm and 8 μm. The polyimide film can have a 60° gloss value equal to or smaller than 10, a haze equal to or higher than 90%, and a Young's modulus equal to or higher than 280 kgf/mm2. In some embodiments, methods of fabricating the polyimide film are also described.

Abstract translation: 聚酰亚胺膜包括形成聚酰亚胺膜的主要分子结构的聚酰亚胺聚合物和以聚酰亚胺膜的总重量的约15重量％至30重量％的重量比存在于聚酰亚胺膜中的聚酰亚胺颗粒，聚酰亚胺颗粒 平均直径约3μm至8μm。 聚酰亚胺膜可以具有等于或小于10的60°光泽值，雾度等于或高于90％，杨氏模量等于或高于280kgf / mm2。 在一些实施例中，还描述了制造聚酰亚胺膜的方法。

公开(公告)号：US08703546B2

公开(公告)日：2014-04-22

申请号：US12784314

申请日：2010-05-20

Applicant: Chih-Wei Lin ,  Ming-Da Cheng ,  Ming-Che Ho ,  Chung-Shi Liu

Inventor： Chih-Wei Lin ,  Ming-Da Cheng ,  Ming-Che Ho ,  Chung-Shi Liu

IPC: H01L21/82 ,  H01L21/288

CPC classification number: H01L21/288 ,  C25D7/123 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11424 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/11901 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/93 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/1146

Abstract: A method of forming a device includes performing a first plating process to form a first metallic feature, and performing an activation treatment to a surface of the first metallic feature in an activation treatment solution, wherein the activation treatment solution includes a treatment agent in de-ionized (DI) water. After the step of performing the activation treatment, performing a second plating process to form a second metallic feature and contacting the surface of the first metallic feature.

Abstract translation: 一种形成装置的方法包括进行第一电镀工艺以形成第一金属特征，并且在活化处理溶液中对第一金属特征的表面进行活化处理，其中活化处理溶液包括处理剂， 电离（DI）水。 在执行激活处理的步骤之后，执行第二电镀处理以形成第二金属特征并接触第一金属特征的表面。

公开(公告)号：US20130309612A1

公开(公告)日：2013-11-21

申请号：US13473695

申请日：2012-05-17

Applicant: Yu-Mei LIU ,  Chin-Hsiang LIN ,  Heng-Hsin LIU ,  Heng-Jen LEE ,  I-Hsiung HUANG ,  Chih-Wei LIN

Inventor： Yu-Mei LIU ,  Chin-Hsiang LIN ,  Heng-Hsin LIU ,  Heng-Jen LEE ,  I-Hsiung HUANG ,  Chih-Wei LIN

IPC: G03F7/20

CPC classification number: G03F7/70358

Abstract: A method and system to improve scanner throughput is provided. An image from a reticle is projected onto a substrate using a continuous linear scanning procedure in which an entire column of die or cells of die is scanned continuously, i.e. without stepping to a different location. Each scan includes translating a substrate with respect to a fixed beam. While the substrate is translated, the reticle is also translated. When a first die or cell of die is projected onto the substrate, the reticle translates along a direction opposite the scan direction and as the scan continues along the same direction, the reticle then translates in the opposite direction of the substrate thereby forming an inverted pattern on the next die or cell. The time associated with exposing the substrate is minimized as the stepping operation only occurs after a complete column of cells is scanned.

Abstract translation: 提供了一种提高扫描仪吞吐量的方法和系统。 使用连续线性扫描程序将来自掩模版的图像投影到基板上，其中连续扫描整列管芯或裸片的单元，即不进入不同的位置。 每个扫描包括相对于固定光束平移衬底。 当底物被翻译时，掩模版也被翻译。 当模具的第一裸片或裸片投影到衬底上时，标线沿着与扫描方向相反的方向平移，并且随着扫描沿着相同的方向继续，标线片然后在衬底的相反方向上平移，从而形成倒置图案 在下一个死亡或细胞。 与曝光底物相关的时间最小化，因为步进操作仅在扫描完整的单元格列之后才发生。

公开(公告)号：US20130093097A1

公开(公告)日：2013-04-18

申请号：US13271952

申请日：2011-10-12

Applicant: Chen-Hua Yu ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Ming-Da Cheng ,  Chih-Wei Lin

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Ming-Da Cheng ,  Chih-Wei Lin

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/31051 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/185 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/48

Abstract: A package-on-package (PoP) structure comprises a first package and a second package. The first package comprises a first die, a second die, and a core material. The core material has a first surface and a second surface. A first redistribution layer (RDL) is on the first surface, and a second RDL is on the second surface. The first die is disposed in the core material between the first surface and the second surface. The second die is coupled to one of the first RDL and the second RDL. The second package comprises a third die and an interposer. The interposer has a first side and a second side. The third die is coupled to the second side of the interposer. The first package is coupled to the second package by first electrical connectors coupled to the second side of the interposer and the first RDL.

Abstract translation: 封装封装（PoP）结构包括第一封装和第二封装。 第一包装包括第一模具，第二模具和芯材料。 芯材料具有第一表面和第二表面。 第一再分配层（RDL）位于第一表面上，第二RDL位于第二表面上。 第一模具设置在第一表面和第二表面之间的芯材料中。 第二管芯耦合到第一RDL和第二RDL之一。 第二包装包括第三管芯和插入件。 插入器具有第一侧和第二侧。 第三裸片耦合到插入器的第二侧。 第一封装通过耦合到插入件的第二侧和第一RDL的第一电连接器耦合到第二封装。

公开(公告)号：US20120181669A1

公开(公告)日：2012-07-19

申请号：US13409517

申请日：2012-03-01

Applicant: Chin-Ming LIN ,  Chia-hung Huang ,  Chi-Ming Yang ,  Chin-Hsiang Lin ,  Yung-Cheng Chen ,  Chih-Wei Lin

Inventor： Chin-Ming LIN ,  Chia-hung Huang ,  Chi-Ming Yang ,  Chin-Hsiang Lin ,  Yung-Cheng Chen ,  Chih-Wei Lin

IPC: H01L23/544 ,  G06F17/50

CPC classification number: G03F7/70433

Abstract: A method includes establishing an initial shot layout in which a number of shots are arranged in vertically aligned columns and horizontally aligned rows to cover a semiconductor wafer. At least one of a row of shots or a column of shots is shifted relative to an adjacent row or column of shots to establish at least one additional shot layout that differs from the initial shot layout in that shots in the at least one shifted row or column of shots are not aligned with the shots in the adjacent row or column of shots with which they were aligned in the initial shot layout. One of the initial shot layout and the at least one additional shot layout is selected as a final shot layout. The wafer is exposed to light using the final shot layout.

Abstract translation: 一种方法包括建立初始照片布局，其中多个照片布置在垂直排列的列和水平排列的行中以覆盖半导体晶片。 一排照片或一列照片中的至少一列相对于相邻的行或列发射位移，以建立与至少一个移位行中的拍摄中的初始镜头布局不同的至少一个附加镜头布局，或 一列照片不与在初始镜头布局中对齐的相邻行或照片列中的镜头对齐。 选择初始镜头布局和至少一个附加镜头布局之一作为最终镜头布局。 使用最终镜头布局将晶片曝光。

公开(公告)号：US20120105776A1

公开(公告)日：2012-05-03

申请号：US13073013

申请日：2011-03-28

Applicant: CHIH-WEI LIN ,  Min-Cheng Wang ,  Chih-Yu Hsu

Inventor： CHIH-WEI LIN ,  Min-Cheng Wang ,  Chih-Yu Hsu

IPC: G02F1/1335 ,  H01J9/26

CPC classification number: G02F1/1339 ,  G02F2001/13415

Abstract: A liquid crystal display panel includes a transistor array substrate, a color filter substrate, a liquid crystal layer, and a sealant material. The transistor array substrate includes a transparent substrate, a transistor array, and a plurality of peripheral wires. The transparent substrate has a display region and a non-display region, and the non-display region is located beside the display region. The transistor array is disposed in the display region. The peripheral wires are disposed in the non-display region and electrically connected with the transistor array. A transmittance of the non-display region is less than 30%. The liquid crystal layer is disposed between the color filter substrate and the transistor array substrate. The sealant material is disposed in the non-display region and connected between the color filter substrate and the transistor array substrate. The sealant material surrounds the liquid crystal layer.

Abstract translation: 液晶显示面板包括晶体管阵列基板，滤色器基板，液晶层和密封材料。 晶体管阵列基板包括透明基板，晶体管阵列和多个外围导线。 透明基板具有显示区域和非显示区域，非显示区域位于显示区域的旁边。 晶体管阵列设置在显示区域中。 外围导线配置在非显示区域并与晶体管阵列电连接。 非显示区域的透射率小于30％。 液晶层设置在滤色器基板和晶体管阵列基板之间。 密封剂材料设置在非显示区域中并且连接在滤色器基板和晶体管阵列基板之间。 密封材料围绕着液晶层。

公开(公告)号：US20120007228A1

公开(公告)日：2012-01-12

申请号：US12832231

申请日：2010-07-08

Applicant: Wen-Hsiung LU ,  Ming-Da CHENG ,  Chih-Wei LIN ,  Ming-Che HO ,  Chung-Shi LIU

Inventor： Wen-Hsiung LU ,  Ming-Da CHENG ,  Chih-Wei LIN ,  Ming-Che HO ,  Chung-Shi LIU

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11424 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13647 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2224/13655 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the disclosure includes a conductive pillar on a semiconductor die. A substrate is provided. A bond pad is over the substrate. A conductive pillar is over the bond pad. The conductive pillar has a top surface, edge sidewalls and a height. A cap layer is over the top surface of the conductive pillar. The cap layer extends along the edge sidewalls of the conductive pillar for a length. A solder material is over a top surface of the cap layer.

Abstract translation: 本公开的实施例包括半导体管芯上的导电柱。 提供基板。 焊盘在衬底上。 导电支柱位于接合垫上方。 导电柱具有顶表面，边缘侧壁和高度。 覆盖层在导电柱的顶表面之上。 盖层沿着导电柱的边缘侧壁延伸一段长度。 焊料材料在覆盖层的顶表面之上。