A method including fabricating a multi-tiered structure to form a compact, resilient interconnect structure. Fabricating each tier or leaf includes, in one aspect, providing a base substrate material, and applying a masking material over the base substrate material. An opening is patterned in the masking material and a resilient element is formed in the opening. A resilient element is coupled to the resilient element to form the resulting product. The method includes repeating this process one or more times to fabricate a chip-level interconnection element. The interconnection element fabricated, in another aspect, is of a size suitable for contacting a packaged semiconductor device, such as in an LGA package.