公开(公告)号：US09466538B1

公开(公告)日：2016-10-11

申请号：US14951634

申请日：2015-11-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Spyridon Skordas ,  Subramanian S Iyer ,  Donald Francis Canaperi ,  Shidong Li ,  Wei Lin

IPC: H01L21/30 ,  H01L21/66 ,  H01L25/00 ,  H01L23/00 ,  H01L21/687 ,  H01L21/68 ,  H01L21/18 ,  H01L21/20

CPC classification number: H01L21/2007 ,  H01L21/187 ,  H01L21/67092 ,  H01L21/67248 ,  H01L21/67288 ,  H01L21/68 ,  H01L21/681 ,  H01L22/12 ,  H01L22/20 ,  H01L24/33 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/27849 ,  H01L2224/83097 ,  H01L2224/83123 ,  H01L2224/83125 ,  H01L2224/83136 ,  H01L2224/83895

Abstract: A method of improving chip-to-chip alignment accuracy for circuitry-including wafer-to-wafer bonding. The method comprises providing separate stages for holding first and second circuitry-including wafers, each stage including a plurality of adjacent thermal actuators arranged in an array integrated with the stage; determining planar distortions of a bonding surface of the first and second circuitry-including wafers; mapping the planar distortions for each wafer based on the relative planar distortions thereon; deducing necessary local thermal expansion measurements for each wafer to compensate for the relative distortions based on the mapping; translating the thermal expansion measurements into a non-uniform wafer temperature profile model and a local heat flux profile model for each wafer; aligning the first and second wafers; and bonding the first and second wafers together. The bonding process includes simultaneously thermally treating at least one of the wafers in situ by individually adjusting the temperature of one or more thermal actuators in the array in accordance with the wafer temperature profile model and the local heat flux model to induce thermal expansion over a surface area corresponding to the dimensions of each adjusted thermal actuator.

Abstract translation: 一种提高芯片对芯片对准精度的方法，包括晶片与晶片的接合。 该方法包括提供用于保持包括第一和第二电路的晶片的分开的级，每个级包括多个相邻的热致动器，其布置成与该级一体化的阵列; 确定包含第一和第二电路的晶片的接合表面的平面失真; 基于其上的相对平面失真来映射每个晶片的平面失真; 推导每个晶片必要的局部热膨胀测量，以补偿基于映射的相对失真; 将热膨胀测量值转换为不均匀的晶片温度分布模型和每个晶片的局部热通量分布模型; 对准第一和第二晶片; 以及将所述第一和第二晶片结合在一起。 接合过程包括通过根据晶片温度分布模型和局部热通量模型单独调节阵列中的一个或多个热致动器的温度来同时热处理至少一个晶片，以在表面上引起热膨胀 面积对应于每个调节热致动器的尺寸。

公开(公告)号：US09412912B2

公开(公告)日：2016-08-09

申请号：US14952227

申请日：2015-11-25

Applicant: PLAYNITRIDE INC.

Inventor： Ching-Liang Lin ,  Yu-Hung Lai ,  Tzu-Yang Lin ,  Pei-Hsin Chen

IPC: H01L21/00 ,  H01L33/48 ,  H01L23/00 ,  H01L25/075 ,  H01L33/62 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L24/83 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0753 ,  H01L33/0095 ,  H01L33/62 ,  H01L2221/68354 ,  H01L2221/68381 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/83001 ,  H01L2224/83136 ,  H01L2224/83143 ,  H01L2224/83192 ,  H01L2224/83805 ,  H01L2224/95085 ,  H01L2224/95136 ,  H01L2224/95146 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2924/0105 ,  H01L2924/01032 ,  H01L2924/01049

Abstract: A method for transferring light-emitting elements onto a package substrate includes: providing a light-emitting unit including a temporary substrate and light-emitting elements; disconnecting the light-emitting elements from the temporary substrate to allow the light-emitting elements to float on a fluid; adjusting spacings between the light-emitting elements to have a predetermined size by controlling flow of the fluid; placing a package substrate into the fluid, followed by aligning the light-emitting elements with connecting pads of the package substrate so as to correspondingly place the light-emitting elements on the connecting pads; and removing the package substrate with the light-emitting elements from the fluid.

Abstract translation: 将发光元件转印到封装衬底上的方法包括：提供包括临时衬底和发光元件的发光单元; 将发光元件与临时衬底断开以允许发光元件漂浮在流体上; 通过控制流体的流动来调节发光元件之间的间隔以具有预定的尺寸; 将封装衬底放置在流体中，然后将发光元件与封装衬底的连接焊盘对准，以便相应地将发光元件放置在连接焊盘上; 以及从所述流体中用所述发光元件去除所述封装衬底。

公开(公告)号：US20150131240A1

公开(公告)日：2015-05-14

申请号：US14402095

申请日：2012-05-22

Applicant: Jan Kostelnik

Inventor： Jan Kostelnik

IPC: B32B37/14 ,  A61N1/375 ,  H04R25/00 ,  A61M5/142 ,  H05K1/18 ,  H05K1/09 ,  B32B38/10 ,  A61N1/362

CPC classification number: B32B37/144 ,  A61M5/14276 ,  A61M2205/0244 ,  A61N1/362 ,  A61N1/375 ,  B32B38/10 ,  B32B2305/80 ,  B32B2307/202 ,  F04C2270/0421 ,  H01L21/4832 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/1329 ,  H01L2224/13298 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/16245 ,  H01L2224/27312 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29388 ,  H01L2224/29499 ,  H01L2224/32245 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/8184 ,  H01L2224/83104 ,  H01L2224/83121 ,  H01L2224/83136 ,  H01L2224/83138 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83204 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/8384 ,  H01L2224/83874 ,  H01L2224/83907 ,  H01L2224/83951 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/15798 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H04R25/606 ,  H05K1/09 ,  H05K1/189 ,  H05K2203/1131 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/2919 ,  H01L2924/07802 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The invention concerns a method for production of electronic assembly (1) with1.1 Supply of an electrically-conducting film (3), especially a support film (3a),1.2 Supply of at least one electrical component (5) with at least one electrical contact site (5c),1.3 Application of an adhesive (20) between the electrical component and a surface (30) of the electrically-conducting film,1.4 Arrangement of the at least one component (5) with the at least one electrical contact site (5c) on the surface (30) of the electrically-conducting film (3) and fastening of the at least one component by formation of an adhesive joint between the electrical component and the surface,1.5 Supply of the support (9), especially from a flexible material,1.6 Lamination of the film (3) with support (9) so that the at least one electrical component (5) is arranged between film (3) and support (9) and formation of a mechanical and electrical connection (23) between the electrical contact site of the at least one electrical component (5) and the electrically-conducting film (3) by low-temperature sintering of nanoparticles, especially from gold, silver, nickel or copper or from an alloy of these metals, in which lamination of the film occurs simultaneously with low-temperature sintering,1.7 Structuring of the electrically-conducting film (3) to conductor tracks (11) and/or cooling surfaces (13).

Abstract translation: 本发明涉及一种用于生产电子组件（1）的方法，其中提供导电薄膜（3），特别是支撑薄膜（3a），1.2提供至少一个电气部件（5），其具有至少一个电气 接触部位（5c），1.3在电气部件和导电膜的表面（30）之间施加粘合剂（20），1.4将至少一个部件（5）与至少一个电接触部位 （3）的表面（30）上的（5c），并且通过在电气部件和表面之间形成粘合剂接头来紧固至少一个部件，1.5提供支撑件（9），尤其是 由柔性材料制成的薄膜（3）与支撑体（9）的层压，使得至少一个电气部件（5）被布置在膜（3）和支撑件（9）之间并形成机械和电连接 23）至少电接触部位之间 一个电子部件（5）和导电膜（3）通过低温烧结纳米颗粒，特别是金，银，镍或铜或这些金属的合金进行低温烧结，其中膜的层压同时发生低 - 导热膜（3）与导体轨道（11）和/或冷却表面（13）的结构。

公开(公告)号：US20150108615A1

公开(公告)日：2015-04-23

申请号：US14059302

申请日：2013-10-21

Applicant: Oracle International Corporation

Inventor： Michael H. S. Dayringer ,  R. David Hopkins ,  Alex Chow

IPC: H01L25/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/72 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16135 ,  H01L2224/16151 ,  H01L2224/1703 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/32145 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/75705 ,  H01L2224/7598 ,  H01L2224/81007 ,  H01L2224/81129 ,  H01L2224/81141 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/81898 ,  H01L2224/819 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83136 ,  H01L2224/83193 ,  H01L2224/8385 ,  H01L2224/92143 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/37001

Abstract: An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a pair of stepped terraces that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package.

Abstract translation: 描述了使用组装部件组装芯片封装的组装部件和技术。 该芯片封装包括沿垂直方向布置成堆叠的一组半导体管芯，它们在水平方向彼此偏移以在垂直堆叠的一侧限定阶梯式台阶。 此外，可以使用组件部件组装芯片封装。 特别地，组装部件可以包括一对阶梯式台阶，其大致镜像芯片封装的阶梯式台阶，并且为组装工具提供垂直位置参考，该组装工具在组装芯片封装期间将该组半导体管芯定位在垂直堆叠中 。

公开(公告)号：US08900923B2

公开(公告)日：2014-12-02

申请号：US13845686

申请日：2013-03-18

Applicant: Micron Technology, Inc.

Inventor： See Hiong Leow ,  Liang Chee Tay

IPC: H01L21/58 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/49 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/29007 ,  H01L2224/29036 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83136 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/191 ,  H01L2924/386 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Packaged microelectronic devices and methods of manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a stand-off layer over a plurality of microelectronic dies on a semiconductor workpiece, and removing selected portions of the stand-off layer to form a plurality of stand-offs with the individual stand-offs positioned on a backside of a corresponding die. The method further includes cutting the semiconductor workpiece to singulate the dies, and attaching the stand-off on a first singulated die to a second die.

Abstract translation: 封装的微电子器件和制造封装的微电子器件的方法在本文中公开。 在一个实施例中，一种制造微电子器件的方法包括在半导体工件上的多个微电子管芯上方形成一个隔离层，并且移除该隔离层的选定部分以与该个体形成多个对立 位于相应模具背面的支架。 该方法还包括切割半导体工件以分割模具，以及将第一单模模具上的支架连接到第二模具。

公开(公告)号：US08888504B2

公开(公告)日：2014-11-18

申请号：US13264892

申请日：2010-03-26

Applicant: Erich Pischler

Inventor： Erich Pischler

IPC: H01R12/00 ,  H01L23/00 ,  H05K1/18 ,  H01L23/498 ,  H05K1/02 ,  H01R24/40 ,  H01R103/00 ,  H01R24/38

CPC classification number: H01L24/10 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/72 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2223/6622 ,  H01L2224/0401 ,  H01L2224/05578 ,  H01L2224/13 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/16106 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81898 ,  H01L2224/83136 ,  H01L2224/83851 ,  H01L2224/90 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01R23/26 ,  H01R24/40 ,  H01R2103/00 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/184 ,  H05K2201/09036 ,  H05K2201/092 ,  H05K2201/09809 ,  H05K2201/09845 ,  Y10T29/49117 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A male connection component (120) for connection with a correspondingly configured female connection component (140) having a recess (144) extending into a main surface (170) of a female Substrate (142) of the female connection component (140), wherein the female connection component (140) comprises a plurality of electrically conductive female contacts (146) which are electrically decoupled from one another and are arranged at different height levels with regard to the main surface (170) of the female Substrate (142), the male connection component (120) comprising a male Substrate (102), a Protrusion (104) protruding from a main surface (160) of the male Substrate (102) and comprising a plurality of electrically conductive male contacts (106) which are electrically decoupled from one another and are arranged at different height levels with regard to the main surface (160) of the male Substrate (102), wherein the male connection component (120) is adapted for connection with the female connection component (140) so that upon connection, each of the plurality of electrically conductive male contacts (106) is brought in contact with one of the plurality of electrically conductive female contacts (146) for providing electric contactation at different height levels, wherein the male Substrate (102) forms at least part of one of a chip, a chip package and a circuit board.

Abstract translation: 用于与相应配置的阴连接部件（140）连接的阳连接部件（120），该阴连接部件具有延伸到阴连接部件（140）的阴基板（142）的主表面（170）的凹部（144），其中 阴连接部件（140）包括多个导电阴触头（146），它们彼此电分离并相对于阴基板（142）的主表面（170）布置在不同的高度水平处， 阳连接部件（120），包括阳基底（102），从阳基底（102）的主表面（160）突出的突起（104），并且包括多个导电的阳触头（106），电接头 并且相对于阳性基板（102）的主表面（160）布置在不同的高度水平处，其中阳连接部件（120）适于与阴连接 连接部件（140），使得在连接时，多个导电阳触头（106）中的每一个与多个导电阴触头（146）中的一个接触，用于在不同的高度级别提供电接触，​​其中 阳基板（102）形成芯片，芯片封装和电路板之一的至少一部分。

公开(公告)号：US08646173B2

公开(公告)日：2014-02-11

申请号：US12712640

申请日：2010-02-25

Applicant: Tohru Nakagawa ,  Hideo Torii

Inventor： Tohru Nakagawa ,  Hideo Torii

IPC: H05K3/20 ,  H05K3/30

CPC classification number: H01L24/83 ,  H01L21/67144 ,  H01L24/75 ,  H01L24/95 ,  H01L25/0655 ,  H01L2224/2919 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/95085 ,  H01L2224/95102 ,  H01L2224/95146 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01052 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49155 ,  Y10T156/10 ,  H01L2924/00

Abstract: A method for mounting an electronic circuit-constituting member on a substrate. The method includes preparing a substrate having a surface comprising a liquid-attracting first region and a liquid-repelling second region that surrounds the first region. The method also includes bringing water into contact with the surface of the substrate so as to dispose said water only on the said first region. The method further includes subjecting said substrate to a member-containing liquid that includes an organic solvent where an electronic circuit-constituting member are dispersed in the organic solvent to move said electronic circuit-constituting member to said water disposed on the said first region. The surface of the member is chemically modified with a silane coupling agent including a group with a C—Cl bond. Also, the method includes removing the water and the organic solvent from the surface of the substrate to mount said electronic circuit-constituting member on said substrate.

Abstract translation: 一种将电子电路构成部件安装在基板上的方法。 该方法包括制备具有包括吸液第一区域和包围第一区域的排液性第二区域的表面的基材。 该方法还包括使水与基底的表面接触，以将所述水仅仅放置在所述第一区域上。 所述方法还包括使所述衬底经受含有有机溶剂的构件的液体，其中电子电路构成构件分散在有机溶剂中，以将所述电子电路构成构件移动到设置在所述第一区域上的所述水。 用包括具有C-Cl键的基团的硅烷偶联剂对构件的表面进行化学改性。 此外，该方法包括从基板的表面除去水和有机溶剂，以将所述电子电路构成部件安装在所述基板上。

公开(公告)号：US20130137215A1

公开(公告)日：2013-05-30

申请号：US13305135

申请日：2011-11-28

Applicant: Alexander Ciliox ,  Georg Borghoff ,  Torsten Groening ,  Karsten Guth

Inventor： Alexander Ciliox ,  Georg Borghoff ,  Torsten Groening ,  Karsten Guth

IPC: H01L21/50 ,  B32B37/00

CPC classification number: H01L25/072 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/75754 ,  H01L2224/83005 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/8384 ,  H01L2924/1203 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  Y10T156/1744 ,  H01L2924/00

Abstract: A die fixing method is disclosed which includes providing a substrate having a metallized surface, forming a joining material on the metallized surface and placing a die alignment member with a plurality of openings on the substrate so that portions of the joining material are exposed through the openings. The method further includes placing a plurality of dies in the openings of the die alignment member with a bottom side of each die in contact with part of the joining material and attaching the plurality of dies to the metallized surface of the substrate at an elevated temperature and pressure, the die alignment member withstanding the elevated temperature and pressure. The die alignment member is removed from the substrate after the plurality of dies are attached to the metallized surface of the substrate.

Abstract translation: 公开了一种芯片定影方法，其包括提供具有金属化表面的基板，在金属化表面上形成接合材料，并将具有多个开口的模具对准部件放置在基板上，使得接合材料的部分通过开口 。 该方法还包括将多个模具放置在模具对准构件的开口中，每个模具的底侧与部分接合材料接触并将多个模具在升高的温度下附着到衬底的金属化表面， 压力，模具对准构件承受升高的温度和压力。 在将多个管芯附着到衬底的金属化表面上之后，从衬底去除管芯对准构件。

公开(公告)号：US08247908B2

公开(公告)日：2012-08-21

申请号：US12843251

申请日：2010-07-26

Applicant: Yao-Sheng Lin ,  Tai-Hong Chen

Inventor： Yao-Sheng Lin ,  Tai-Hong Chen

IPC: H01L23/52

CPC classification number: H05K3/361 ,  G02F1/13452 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/81 ,  H01L24/83 ,  H01L24/98 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/13016 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/81903 ,  H01L2224/83101 ,  H01L2224/83136 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0781 ,  H01L2924/12044 ,  H01L2924/15788 ,  H01L2924/351 ,  H05K1/111 ,  H05K3/225 ,  H05K3/323 ,  H05K3/4092 ,  H05K2201/09427 ,  H05K2201/09663 ,  H05K2203/175 ,  H01L2924/00

Abstract: A circuit substrate and the method for fabricating a packaging of the circuit substrate are provided. A plurality of electrodes are formed on the surface of the circuit substrate, the electrodes are formed with fork structures over an connection section of the circuit substrate, so that when the circuit substrate expands/contracts due to thermal processes, the probability of alignment with electrodes of an external circuit board is increased by easily detaching the fork structure overlapping an electrode of the external circuit board which is not corresponding to the fork structure of the electrode of the circuit substrate, so as to avoid short circuit. Thus, electrode misalignment due to electrode pitch variation of the traditional circuit substrate as a result of thermal deformation can be effectively eliminated.

Abstract translation: 提供电路基板和制造电路基板的封装的方法。 多个电极形成在电路基板的表面上，电极在电路基板的连接部分上形成有叉结构，使得当电路基板由于热处理而膨胀/收缩时，与电极对准的概率 通过容易地分离与外部电路板的与电路基板的电极的叉结构不相对应的电极重叠的叉结构来增加外部电路板，以避免短路。 因此，可以有效地消除由于热变形导致的传统电路基板的电极间距变化引起的电极未对准。

公开(公告)号：US08211788B2

公开(公告)日：2012-07-03

申请号：US12486771

申请日：2009-06-18

Applicant: Shyh-Ming Chang ,  Sheng-Shu Yang

Inventor： Shyh-Ming Chang ,  Sheng-Shu Yang

IPC: H01L21/44

CPC classification number: H01L21/563 ,  H01L23/295 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/13562 ,  H01L2224/136 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/29287 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/83136 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/838 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/9211 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H05K3/305 ,  H05K3/361 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/10977 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method of fabricating a bonding structure having compliant bumps includes first providing a first substrate and a second substrate. The first substrate includes first bonding pads. The second substrate is disposed on one side of the first substrate and includes second bonding pads and compliant bumps disposed thereon. The second bonding pads are opposite to the first bonding pads. Next, a non-conductive adhesive layer and ball-shaped spacers are formed between the first and the second substrates. Finally, the first substrate, the non-conductive adhesive layer, and the second substrate are compressed, such that the compliant bumps on the second bonding pads of the second substrate pass through the non-conductive adhesive layer and are electrically connected to the first bonding pads of the first substrate, respectively. The ball-shaped spacers are distributed in the non-conductive adhesive layer sandwiched between the first and the second substrates for maintaining the gap therebetween.

Abstract translation: 制造具有柔顺凸块的接合结构的方法包括首先提供第一基板和第二基板。 第一衬底包括第一接合焊盘。 第二基板设置在第一基板的一侧，并且包括设置在其上的第二接合焊盘和顺应凸块。 第二接合焊盘与第一接合焊盘相对。 接下来，在第一和第二基板之间形成非导电粘合剂层和球形间隔物。 最后，第一基板，非导电粘合剂层和第二基板被压缩，使得第二基板的第二接合焊盘上的顺从凸块穿过非导电粘合剂层，并且电连接到第一接合 第一基板的焊盘。 球形间隔件分布在夹在第一和第二基板之间的非导电粘合剂层中，以保持它们之间的间隙。