公开(公告)号：US09466538B1

公开(公告)日：2016-10-11

申请号：US14951634

申请日：2015-11-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Spyridon Skordas ,  Subramanian S Iyer ,  Donald Francis Canaperi ,  Shidong Li ,  Wei Lin

IPC: H01L21/30 ,  H01L21/66 ,  H01L25/00 ,  H01L23/00 ,  H01L21/687 ,  H01L21/68 ,  H01L21/18 ,  H01L21/20

CPC classification number: H01L21/2007 ,  H01L21/187 ,  H01L21/67092 ,  H01L21/67248 ,  H01L21/67288 ,  H01L21/68 ,  H01L21/681 ,  H01L22/12 ,  H01L22/20 ,  H01L24/33 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/27849 ,  H01L2224/83097 ,  H01L2224/83123 ,  H01L2224/83125 ,  H01L2224/83136 ,  H01L2224/83895

Abstract: A method of improving chip-to-chip alignment accuracy for circuitry-including wafer-to-wafer bonding. The method comprises providing separate stages for holding first and second circuitry-including wafers, each stage including a plurality of adjacent thermal actuators arranged in an array integrated with the stage; determining planar distortions of a bonding surface of the first and second circuitry-including wafers; mapping the planar distortions for each wafer based on the relative planar distortions thereon; deducing necessary local thermal expansion measurements for each wafer to compensate for the relative distortions based on the mapping; translating the thermal expansion measurements into a non-uniform wafer temperature profile model and a local heat flux profile model for each wafer; aligning the first and second wafers; and bonding the first and second wafers together. The bonding process includes simultaneously thermally treating at least one of the wafers in situ by individually adjusting the temperature of one or more thermal actuators in the array in accordance with the wafer temperature profile model and the local heat flux model to induce thermal expansion over a surface area corresponding to the dimensions of each adjusted thermal actuator.

Abstract translation: 一种提高芯片对芯片对准精度的方法，包括晶片与晶片的接合。 该方法包括提供用于保持包括第一和第二电路的晶片的分开的级，每个级包括多个相邻的热致动器，其布置成与该级一体化的阵列; 确定包含第一和第二电路的晶片的接合表面的平面失真; 基于其上的相对平面失真来映射每个晶片的平面失真; 推导每个晶片必要的局部热膨胀测量，以补偿基于映射的相对失真; 将热膨胀测量值转换为不均匀的晶片温度分布模型和每个晶片的局部热通量分布模型; 对准第一和第二晶片; 以及将所述第一和第二晶片结合在一起。 接合过程包括通过根据晶片温度分布模型和局部热通量模型单独调节阵列中的一个或多个热致动器的温度来同时热处理至少一个晶片，以在表面上引起热膨胀 面积对应于每个调节热致动器的尺寸。

公开(公告)号：US09293439B2

公开(公告)日：2016-03-22

申请号：US14567052

申请日：2014-12-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Edmund Blackshear ,  Elaine Cyr ,  Benjamin Vito Fasano ,  Paul Francis Fortier ,  Marcus E. Interrante ,  Roger Lam ,  Shidong Li ,  Thomas Edward Lombardi ,  Hilton T. Toy ,  Thomas Weiss

IPC: H01L23/00 ,  H01L21/50 ,  H01L23/10 ,  H01L23/367 ,  H01L23/373 ,  H01L23/055 ,  H01L23/42 ,  H01L23/498

CPC classification number: H01L24/83 ,  H01L21/50 ,  H01L23/055 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/29036 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/83862 ,  H01L2924/15311

Abstract: An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is referred to as a lid tie. A lid is placed on the laminate, and is in contact with the lid ties. The lid ties serve to add stability to the laminate and reduce flexing during thermal processing and mechanical stress.