公开(公告)号：US11756829B2

公开(公告)日：2023-09-12

申请号：US17961400

申请日：2022-10-06

Applicant: Intel Corporation

Inventor： Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

IPC: H01L21/768 ,  H01L21/306 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/66 ,  H01L21/28 ,  H01L23/535 ,  H01L29/06 ,  H01L21/32

CPC classification number: H01L21/76897 ,  H01L21/28008 ,  H01L21/30625 ,  H01L21/76805 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66545 ,  H01L21/32

Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

公开(公告)号：US11735647B2

公开(公告)日：2023-08-22

申请号：US17226891

申请日：2021-04-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wang-Chun Huang ,  Hou-Yu Chen ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/423

CPC classification number: H01L29/66795 ,  H01L21/82345 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/7851 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/42392

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes at least one first semiconductor element and at least one second semiconductor element over a substrate, a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element, a first work function metal layer wrapping around each of the at least one first semiconductor element and extending continuously from the at least one first semiconductor element to a top surface of the dielectric fin, and a second work function metal layer disposed over the at least one second semiconductor element and the first work function metal layer.

公开(公告)号：US11705517B2

公开(公告)日：2023-07-18

申请号：US17136185

申请日：2020-12-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xin Miao ,  Kangguo Cheng ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/762 ,  H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L21/265 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L29/7843 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/0262 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116

Abstract: A method of fabricating a semiconductor device is described. The method includes forming a nanosheet stack on a substrate, the nanosheet stack includes nanosheet channel layers. A gate is formed around the nanosheet channel layers of the nanosheet stack. A strained material is formed along a sidewall surface of the gate. The strained material is configured to create strain in the nanosheet channel layers of the nanosheet stack.

公开(公告)号：US11705336B2

公开(公告)日：2023-07-18

申请号：US17682643

申请日：2022-02-28

Applicant: SK hynix Inc.

Inventor： Yunhyuck Ji

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/28229 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823857

Abstract: A method for fabricating a semiconductor device includes forming a deposition-type interface layer over a substrate, converting the deposition-type interface layer into an oxidation-type interface layer, forming a high-k layer over the oxidation-type interface layer, forming a dipole interface on an interface between the high-k layer and the oxidation-type interface layer, forming a conductive layer over the high-k layer, and patterning the conductive layer, the high-k layer, the dipole interface, and the oxidation-type interface layer to form a gate stack over the substrate.

公开(公告)号：US20230223304A1

公开(公告)日：2023-07-13

申请号：US17662940

申请日：2022-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Tai-Chun Huang

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/423

CPC classification number: H01L21/823418 ,  H01L21/31116 ,  H01L29/42392 ,  H01L21/823437 ,  H01L21/823468

Abstract: A method includes forming a first gate stack over a first semiconductor region, depositing a spacer layer on the first gate stack, and depositing a dummy spacer layer on the spacer layer. The dummy spacer layer includes a metal-containing material. An anisotropic etching process is performed on the dummy spacer layer and the spacer layer to form a gate spacer and a dummy sidewall spacer, respectively. The first semiconductor region is etched to form a recess extending into the first semiconductor region. The first semiconductor region is etched using the first gate stack, the gate spacer, and the dummy sidewall spacer as an etching mask. The method further includes epitaxially growing a source/drain region in the recess, and removing the dummy sidewall spacer after the source/drain region is grown.

公开(公告)号：US20230207664A1

公开(公告)日：2023-06-29

申请号：US18116721

申请日：2023-03-02

Applicant: Intel Corporation

Inventor： Michael L. HATTENDORF ,  Curtis WARD ,  Heidi M. MEYER ,  Tahir GHANI ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H10B10/00 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167

CPC classification number: H01L29/66545 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7843 ,  H01L27/0886 ,  H01L21/76232 ,  H01L29/6656 ,  H01L29/0653 ,  H01L21/823431 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L21/76816 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785 ,  H01L29/165 ,  H01L21/76846 ,  H01L21/76849 ,  H01L29/7845 ,  H01L21/76834 ,  H01L29/41791 ,  H01L21/76801 ,  H10B10/12 ,  H01L29/0649 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5283 ,  H01L23/53266 ,  H01L27/0924 ,  H01L28/24 ,  H01L29/0847 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/7854 ,  H01L21/28518 ,  H01L23/5329 ,  H01L27/0207 ,  H01L28/20 ,  H01L29/41783 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823828 ,  H01L23/528 ,  H01L27/0922 ,  H01L29/167 ,  H01L29/66636 ,  H01L29/7851 ,  H01L21/76883 ,  H01L21/76885 ,  H01L29/665 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.

公开(公告)号：US20230207569A1

公开(公告)日：2023-06-29

申请号：US18111313

申请日：2023-02-17

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Jeng-Ya D. YEH ,  Curtis TSAI ,  Joodong PARK ,  Chia-Hong JAN ,  Gopinath BHIMARASETTI

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L27/1211 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/66545 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L29/6681 ,  H01L29/51 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823437 ,  H01L29/513 ,  H01L29/42356 ,  H01L21/0228 ,  H01L21/02164 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/6656

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US20230197719A1

公开(公告)日：2023-06-22

申请号：US18168332

申请日：2023-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Woo Noh ,  Jae-Hyeoung Ma ,  Dong-Il Bae

IPC: H01L27/088 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L27/0886 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/1033 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823468 ,  H01L21/823412 ,  H01L21/02532 ,  H01L21/3086

Abstract: A semiconductor device may include first channels on a first region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, second channels on a second region of the substrate and spaced apart from each other in the vertical direction, a first gate structure on the first region of the substrate and covering at least a portion of a surface of each of the first channels, and a second gate structure on the second region of the substrate and covering at least a portion of a surface of each of the second channels. The second channels may be disposed at heights substantially the same as those of corresponding ones of the first channels, and a height of a lowermost one of the second channels may be greater than a height of a lowermost one of the first channels.

公开(公告)号：US20230197522A1

公开(公告)日：2023-06-22

申请号：US18065130

申请日：2022-12-13

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Anne Vandooren ,  Julien Ryckaert ,  Naoto Horiguchi

IPC: H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/42392

Abstract: The disclosure relates to a method for forming a semiconductor device. The method includes forming a device layer stack on a substrate, the device layer stack having a first sub-stack comprising a first sacrificial layer and on the first sacrificial layer a channel layer defining a topmost layer of the first sub-stack, and a second sub-stack on the first sub-stack and including a first sacrificial layer defining a bottom layer of the second sub-stack, and a second sacrificial layer on the first sacrificial layer, wherein said first sacrificial layers are formed of a first sacrificial semiconductor material, the second sacrificial layer is formed of a second sacrificial semiconductor material, and the channel layer is formed of a semiconductor channel material, and wherein a thickness of the second sub-stack exceeds a thickness of the first sacrificial layer of the first sub-stack. The method comprises replacing the second sacrificial layer of the second sub-stack with a dielectric layer; forming recesses in the device layer stack by laterally etching back end surfaces of the first sacrificial layers of the first and second sub-stacks from opposite sides of the sacrificial gate structure; and forming inner spacers in the recesses.

公开(公告)号：US20230187281A1

公开(公告)日：2023-06-15

申请号：US18167100

申请日：2023-02-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Lo-Heng Chang ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Jung-Hung Chang ,  Pei-Hsun Wang

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L21/762 ,  H01L29/10

CPC classification number: H01L21/823431 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/66636 ,  H01L21/30604 ,  H01L21/3086 ,  H01L29/6653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L21/823437 ,  H01L27/0886 ,  H01L21/823481 ,  H01L21/76224 ,  H01L29/66545 ,  H01L29/6656 ,  H01L21/823468 ,  H01L29/1037 ,  H01L21/823418

Abstract: A semiconductor device includes a substrate, a plurality of nanosheets, a plurality of source/drain (S/D) features, and a gate stack. The substrate includes a first fin and a second fin. The first fin has a first width less than a second width of the second fin. The plurality of nanosheets is disposed on the first fin and the second fin. The plurality of source/drain (S/D) features are located on the first fin and the second fin and abutting the plurality of nanosheets. A bottom surface of the plurality of source/drain (S/D) features on the first fin is equal to or lower than a bottom surface of the plurality of source/drain (S/D) features on the second fin. The gate stack wraps each of the plurality of nanosheets.