公开(公告)号：US20140263583A1

公开(公告)日：2014-09-18

申请号：US13866858

申请日：2013-04-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yi-Li Hsiao ,  Da-Yuan Shih ,  Chih-Hang Tung ,  Chen-Hua Yu

IPC: H05K13/04

CPC classification number: H05K13/0465 ,  H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/75102 ,  H01L2224/75251 ,  H01L2224/757 ,  H01L2224/75703 ,  H01L2224/7598 ,  H01L2224/75985 ,  H01L2224/75987 ,  H01L2224/75988 ,  H01L2224/81065 ,  H01L2224/8109 ,  H01L2224/81093 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01013

Abstract: A method includes placing a plurality of first package components over second package components, which are included in a third package component. First metal connectors in the first package components are aligned to respective second metal connectors of the second package components. After the plurality of first package components is placed, a metal-to-metal bonding is performed to bond the first metal connectors to the second metal connectors.

Abstract translation: 一种方法包括将多个第一包装部件放置在包括在第三包装部件中的第二包装部件上。 第一包装部件中的第一金属连接器与第二包装部件的相应的第二金属连接器对准。 在放置多个第一封装部件之后，执行金属对金属接合以将第一金属连接器接合到第二金属连接器。

公开(公告)号：US20140113411A1

公开(公告)日：2014-04-24

申请号：US14136977

申请日：2013-12-20

Applicant: Spansion LLC

Inventor： Naomi MASUDA ,  Masataka HOSHINO ,  Ryota FUKUYAMA

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16105 ,  H01L2224/75252 ,  H01L2224/81054 ,  H01L2224/81065 ,  H01L2224/81191 ,  H01L2224/812 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83907 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A semiconductor device which includes a first semiconductor chip 10, a first electrode 12 formed on the first semiconductor chip 10, a second semiconductor chip 20 to which the first semiconductor chip 10 is mounted, a second electrode 22 with a protrusion 24, which is formed on the second semiconductor chip 20, and a solder bump 14 which bonds the first electrode 12 and the second electrode 22 to cover at least a part of a side surface of the protrusion 24, and a method for manufacturing thereof are provided.

Abstract translation: 一种半导体器件，包括第一半导体芯片10，形成在第一半导体芯片10上的第一电极12，安装有第一半导体芯片10的第二半导体芯片20，形成有突起24的第二电极22，其形成 以及与第一电极12和第二电极22接合以覆盖突起24的侧面的至少一部分的焊料凸点14及其制造方法。

公开(公告)号：US08525278B2

公开(公告)日：2013-09-03

申请号：US13213863

申请日：2011-08-19

Applicant: Chia-Hua Chu ,  Chung-Hsien Lin

Inventor： Chia-Hua Chu ,  Chung-Hsien Lin

IPC: H01L27/20 ,  H01L21/98

CPC classification number: B81C1/00238 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2207/012 ,  H01L23/10 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11622 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/16145 ,  H01L2224/73257 ,  H01L2224/81011 ,  H01L2224/81013 ,  H01L2224/81054 ,  H01L2224/81065 ,  H01L2224/81203 ,  H01L2224/81805 ,  H01L2224/8182 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A method and device having chip scale MEMS packaging is described. A first substrate includes a MEMS device and a second substrate includes an integrated circuit. The frontside of the first substrate is bonded to the backside of the second substrate. Thus, the second substrate provides a cavity to encase, protect or operate the MEMS device within. The bond may provide an electrical connection between the first and second substrate. In an embodiment, a through silicon via is used to carry the signals from the first substrate to an I/O connection on the frontside of the second substrate.

Abstract translation: 描述了具有芯片级MEMS封装的方法和装置。 第一衬底包括MEMS器件，第二衬底包括集成电路。 第一衬底的前侧结合到第二衬底的背面。 因此，第二衬底提供了一个空腔来封装，保护或操作其中的MEMS器件。 该键可以在第一和第二衬底之间提供电连接。 在一个实施例中，穿通硅通孔用于将信号从第一衬底传送到第二衬底的前侧上的I / O连接。

公开(公告)号：US20130181040A1

公开(公告)日：2013-07-18

申请号：US13723771

申请日：2012-12-21

Applicant: Tokyo Electron Limited

Inventor： Shinjiro Watanabe ,  Itaru Iida ,  Muneo Harada

IPC: H01L21/48

CPC classification number: H01L21/4814 ,  H01L21/683 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16145 ,  H01L2224/75101 ,  H01L2224/75272 ,  H01L2224/7598 ,  H01L2224/81011 ,  H01L2224/81065 ,  H01L2224/81075 ,  H01L2224/81139 ,  H01L2224/81815 ,  H01L2924/01007 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Provided is a semiconductor device manufacturing system according to the present disclosure which manufactures a semiconductor device using a chip stack. The system includes a chip reducing apparatus and a chip bonding apparatus, the chip reducing apparatus includes a reduction chamber, an oxide film of the surface of the terminal of each chip is reduced in the reduction chamber, the chip bonding apparatus includes a reflow chamber isolated from the reduction chamber, a solder ball is bonded to the terminal of each chip in the reflow chamber, and the chip bonding apparatus is installed separately from the chip reducing apparatus.

Abstract translation: 提供了根据本公开的半导体器件制造系统，其制造使用芯片堆叠的半导体器件。 该系统包括减芯装置和芯片接合装置，所述减芯装置包括还原室，所述还原室中的每个芯片的端子表面的氧化膜被还原，所述芯片接合装置包括隔离的回流室 从还原室将焊球接合到回流室中的每个芯片的端子，并且芯片接合装置与芯片减少装置分开地安装。

公开(公告)号：US20130175323A1

公开(公告)日：2013-07-11

申请号：US13573486

申请日：2012-09-17

Applicant: Jian ZHANG ,  Chunghsin Lee

Inventor： Jian ZHANG ,  Chunghsin Lee

IPC: H01L21/67

CPC classification number: H01L21/67173 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/206 ,  B23K2101/42 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/81054 ,  H01L2224/81065 ,  H01L2224/8109 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/81205 ,  H01L2224/81211 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A linear, serial chip/substrate assembly processing machine for stepwise advancing a pre-assembled chip/die substrate on a support plate through a series of sealable chambers having displacable bottom processing portions. The process begins at a loading station and ends up at an unloading station after various melting and vacuuming of chip/substrate components supported on a device tray through those various chambers to the final joining thereof.

Abstract translation: 一种用于通过具有可移位的底部处理部分的一系列可密封的室逐步推进预组装的芯片/模具基板在支撑板上的线性，串联芯片/基板组装处理机。 该过程在加载站开始，并且在各种熔融和抽真空处理装置托盘上的芯片/基板部件之后通过那些不同的室进行最后的连接，在卸载站处结束。

公开(公告)号：US08445321B2

公开(公告)日：2013-05-21

申请号：US12887772

申请日：2010-09-22

Applicant: Masatoshi Fukuda

Inventor： Masatoshi Fukuda

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L24/81 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/562 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/11901 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/731 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81007 ,  H01L2224/81065 ,  H01L2224/81097 ,  H01L2224/81194 ,  H01L2224/81815 ,  H01L2224/9212 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In one embodiment, a method of manufacturing a semiconductor device is disclosed. The method includes forming a cured film of an insulation resin on a surface of a first semiconductor chip and flip-chip bonding a second semiconductor via a bump on the first semiconductor chip on which the cured film of the insulation resin is formed. The insulation resin can be cured at temperature range from (A−50)° C. to (A+50)° C., wherein “A” is a solidification point of the bump.

Abstract translation: 在一个实施例中，公开了制造半导体器件的方法。 该方法包括在第一半导体芯片的表面上形成绝缘树脂的固化膜，并且在其上形成有绝缘树脂的固化膜的第一半导体芯片上经由凸块将第二半导体结合到第二半导体。 绝缘树脂可以在（A-50）℃至（A + 50）℃的温度范围内固化，其中“A”是凸点的凝固点。

公开(公告)号：US08252678B2

公开(公告)日：2012-08-28

申请号：US12930203

申请日：2010-12-31

Applicant: Jian Zhang

Inventor： Jian Zhang

IPC: H01L21/44

CPC classification number: B23K3/0623 ,  B23K2101/40 ,  H01L21/67098 ,  H01L21/68764 ,  H01L21/68771 ,  H01L24/11 ,  H01L24/742 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/291 ,  H01L2224/73203 ,  H01L2224/7501 ,  H01L2224/75102 ,  H01L2224/755 ,  H01L2224/7565 ,  H01L2224/758 ,  H01L2224/81065 ,  H01L2224/8109 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81205 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81948 ,  H01L2224/81986 ,  H01L2224/83065 ,  H01L2224/8309 ,  H01L2224/83193 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2224/83948 ,  H01L2224/83986 ,  H01L2224/9205 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: A serial thermal processing arrangement for treating a pre-assembled chip/wafer assembly of semiconductor material in a rotary processor, through a series of intermittent, rotatively advanced, movements into independent, temperature and pressure controlled, circumferentially disposed chambers.

Abstract translation: 一种串行热处理装置，用于通过一系列间歇的，可旋转地前进的运动，将旋转式处理器中的预组装的半导体材料的芯片/晶片组件处理成独立的，温度和压力控制的周向布置的腔室。

公开(公告)号：US07772032B2

公开(公告)日：2010-08-10

申请号：US12292378

申请日：2008-11-18

Applicant: Yoichiro Kurita

Inventor： Yoichiro Kurita

IPC: H01L21/60 ,  H01L21/603

CPC classification number: B23K1/0016 ,  B23K2101/40 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13551 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/27416 ,  H01L2224/27436 ,  H01L2224/27515 ,  H01L2224/27552 ,  H01L2224/2761 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75314 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/81048 ,  H01L2224/81065 ,  H01L2224/8109 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81825 ,  H01L2224/8183 ,  H01L2224/81906 ,  H01L2224/81907 ,  H01L2224/83 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01082 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/16145 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A manufacturing method for manufacturing an electronic device includes a first electronic component and a second electronic component; and a bond part for the first electronic component joined to another bond part for the second electronic component. In a first process of this manufacturing method, the metallic bond part for the first electronic component is placed directly against the metallic bond part for the second electronic component, pressure is applied to the first electronic component and the second electronic component and, after metallically joining the above two bond parts, the pressure applied to the first electronic component and the second electronic component is released. In a second process in the manufacturing method, a clamping member affixes the relative positions of the joined first electronic component and second electronic component, and heats the first electronic component and the second electronic component to maintain a specified temperature.

Abstract translation: 一种电子设备的制造方法，包括：第一电子部件和第二电子部件; 以及与第二电子部件的另一接合部接合的第一电子部件的接合部。 在该制造方法的第一工序中，将第一电子部件的金属接合部直接配置在第二电子部件的金属接合部上，对第一电子部件和第二电子部件施加压力，在金属接合 上述两个粘合部分，释放施加到第一电子部件和第二电子部件的压力。 在制造方法的第二工序中，夹持构件固定连接的第一电子部件和第二电子部件的相对位置，并加热第一电子部件和第二电子部件，以维持规定的温度。

公开(公告)号：US20070125449A1

公开(公告)日：2007-06-07

申请号：US11633419

申请日：2006-12-05

Applicant: Ryoichi Kajiwara ,  Kazutoshi Itou

Inventor： Ryoichi Kajiwara ,  Kazutoshi Itou

IPC: C22C13/02

CPC classification number: C22C13/02 ,  B23K35/02 ,  B23K35/025 ,  B23K35/22 ,  B23K35/262 ,  B23K35/3006 ,  B23K35/302 ,  H01L23/49513 ,  H01L24/01 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/376 ,  H01L2224/40091 ,  H01L2224/40225 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/81065 ,  H01L2224/81075 ,  H01L2224/81097 ,  H01L2224/81805 ,  H01L2224/83065 ,  H01L2224/83075 ,  H01L2224/83097 ,  H01L2224/83203 ,  H01L2224/83211 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/20108 ,  H01L2924/30105 ,  H01L2924/351 ,  Y10T428/12528 ,  Y10T428/12708 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01026 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

Abstract: The present invention intends to provide a power semiconductor device using a high-temperature lead-free solder material, the high-temperature lead-free solder material having the heat resistant property at 280° C. or more, and the bondability at 400° C. or less, and excellent in the suppliabilty and wettability of solder, and in the high-temperature storage reliability and the temperature cycle reliability. In the power semiconductor device according to the present invention, a semiconductor element and a metal electrode member were bonded each other by a high-temperature solder material comprising Sn, Sb, Ag, and Cu as the main constitutive elements and the rest of other unavoidable impurity elements wherein the high-temperature solder material comprises 42 wt %≦Sb/(Sn+Sb)≦48 wt %, 5 wt %≦Ag

Abstract translation: 本发明旨在提供一种使用高温无铅焊料的功率半导体器件，具有280℃以上的耐热性的高温无铅焊料以及400℃下的结合性 或更低，焊料的可供应性和润湿性优异，以及高温存储的可靠性和温度循环的可靠性。 在根据本发明的功率半导体器件中，半导体元件和金属电极构件通过包含Sn，Sb，Ag和Cu的高温焊料作为主要构成元素彼此接合，其余的不可避免的 杂质元素，其中高温焊料材料包含42重量％<= Sb /（Sn + Sb）<= 48重量％，5重量％<= Ag <20重量％，3重量％<= Cu <10重量％ 和Ag + Cu <= 25wt％。

公开(公告)号：US20040233649A1

公开(公告)日：2004-11-25

申请号：US10479735

申请日：2004-06-22

Inventor： Wolfgang Honlein ,  Helmut Klose ,  Hyang-Sook Klose ,  Franz Kreupl ,  Werner Simburger

IPC: H05K007/02

CPC classification number: H01L25/0657 ,  B82Y10/00 ,  B82Y30/00 ,  G01R31/2884 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/13193 ,  H01L2224/16145 ,  H01L2224/81065 ,  H01L2224/81097 ,  H01L2224/81191 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01072 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2224/05552

Abstract: A multiplicity of nanotubes are applied to at least one external chip metal contact of the electronic chip in order to make contact between the electronic chip and a further electronic chip.

Abstract translation: 将多个纳米管应用于电子芯片的至少一个外部芯片金属触点，以便在电子芯片和另一个电子芯片之间进行接触。