公开(公告)号：US08349649B2

公开(公告)日：2013-01-08

申请号：US12905167

申请日：2010-10-15

Applicant: Yoichiro Kurita

Inventor： Yoichiro Kurita

IPC: H01L21/00 ,  H01L21/30 ,  H01L21/46 ,  H01L23/02 ,  H01L21/40 ,  H01L21/48 ,  H01L21/52

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/00

Abstract: A semiconductor device includes a first interposer provided with a first chip first interconnection; a first chip arranged to contact the first interposer in one surface of the first chip; a second interposer arranged to contact the other surface of the first chip and provided with a first chip second interconnection; and a second chip group mounted on the second interposer. The first chip has a circuit forming surface on which a circuit element is formed, as one of the surfaces of the first chip, and the first chip first interconnection and the first chip second interconnection are electrically connected with the circuit element. A through electrode is formed to pass from the one of the surfaces of the first chip to the other surface, and one of the first chip first interconnection and the first chip second interconnection is electrically connected with the circuit element through the through electrode.

Abstract translation: 半导体器件包括具有第一芯片第一互连的第一插入器; 布置成在所述第一芯片的一个表面中接触所述第一插入件的第一芯片; 第二插入器，布置成接触第一芯片的另一表面并且设置有第一芯片第二互连; 以及安装在第二插入器上的第二芯片组。 第一芯片具有形成电路元件的电路形成表面，作为第一芯片的一个表面，并且第一芯片第一互连和第一芯片第二互连电路与电路元件电连接。 通孔形成为从第一芯片的一个表面到另一个表面，并且第一芯片第一互连和第一芯片第二互连中的一个通过贯通电极与电路元件电连接。

公开(公告)号：US08278143B2

公开(公告)日：2012-10-02

申请号：US13067723

申请日：2011-06-22

Applicant: Yoichiro Kurita

Inventor： Yoichiro Kurita

IPC: H01L21/60 ,  H01L21/603

CPC classification number: B23K1/0016 ,  B23K2101/40 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13551 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/27416 ,  H01L2224/27436 ,  H01L2224/27515 ,  H01L2224/27552 ,  H01L2224/2761 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75314 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/81048 ,  H01L2224/81065 ,  H01L2224/8109 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81825 ,  H01L2224/8183 ,  H01L2224/81906 ,  H01L2224/81907 ,  H01L2224/83 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01082 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/16145 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying pressure to the first electronic component and the second electronic component, joining the first metallic bond part to the second metallic bond part with solid-phase diffusion, and releasing the applied pressure, and a second process for heating the first electronic component and the second electronic component at a predetermined temperature such that the first metallic bond part and the second metallic bond part are joined together by melting at least one of the first metallic bond part and the second metallic bond part.

Abstract translation: 接合形成在第一电子部件上的第一金属接合部和形成在第二电子部件上的第二金属接合部的电子设备的制造方法包括：将第一金属接合部直接放置在第二金属接合部上的第一工序， 向所述第一电子部件和所述第二电子部件施加压力，将所述第一金属接合部与所述第二金属接合部以固相扩散接合，释放所施加的压力，以及第二加工所述第一电子部件和所述第二电子部件 电子部件在预定温度下通过熔化第一金属接合部和第二金属接合部中的至少一个而使第一金属接合部和第二金属接合部接合在一起。

公开(公告)号：US20110253767A1

公开(公告)日：2011-10-20

申请号：US13067723

申请日：2011-06-22

Applicant: Yoichiro Kurita

Inventor： Yoichiro Kurita

IPC: H01L21/02 ,  B23K31/02

CPC classification number: B23K1/0016 ,  B23K2101/40 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13551 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/27416 ,  H01L2224/27436 ,  H01L2224/27515 ,  H01L2224/27552 ,  H01L2224/2761 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75314 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/81048 ,  H01L2224/81065 ,  H01L2224/8109 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81825 ,  H01L2224/8183 ,  H01L2224/81906 ,  H01L2224/81907 ,  H01L2224/83 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01082 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/16145 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying pressure to the first electronic component and the second electronic component, joining the first metallic bond part to the second metallic bond part with solid-phase diffusion, and releasing the applied pressure, and a second process for heating the first electronic component and the second electronic component at a predetermined temperature such that the first metallic bond part and the second metallic bond part are joined together by melting at least one of the first metallic bond part and the second metallic bond part.

Abstract translation: 接合形成在第一电子部件上的第一金属接合部和形成在第二电子部件上的第二金属接合部的电子设备的制造方法包括：将第一金属接合部直接放置在第二金属接合部上的第一工序， 向所述第一电子部件和所述第二电子部件施加压力，将所述第一金属接合部与所述第二金属接合部以固相扩散接合，释放所施加的压力，以及第二加工所述第一电子部件和所述第二电子部件 电子部件在预定温度下通过熔化第一金属接合部和第二金属接合部中的至少一个而使第一金属接合部和第二金属接合部接合在一起。

公开(公告)号：US08035231B2

公开(公告)日：2011-10-11

申请号：US12114238

申请日：2008-05-02

Applicant: Yoichiro Kurita ,  Masaya Kawano ,  Koji Soejima

Inventor： Yoichiro Kurita ,  Masaya Kawano ,  Koji Soejima

IPC: H01L23/48

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/83051 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19041 ,  H05K3/4644 ,  H05K3/4676 ,  H05K3/4688 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2224/0401

Abstract: The semiconductor device 1 includes interconnect layers 10, 20, an IC chip 30, via plugs 42, 44, a seal resin 50, and solder balls 60. The interconnect layer 10 includes a via plug 42. An end face of the via plug 42 on the side of the interconnect layer 20 is smaller in area than the opposite end face, i.e. the end face on the side of the IC chip 30. An end face of the via plug 44 on the side of the interconnect layer 10 is smaller in area than the opposite end face, i.e. the end face on the side of the solder balls 60. The thermal decomposition temperature of the insulating resin 14 constituting the interconnect layer 10 is higher than that of the insulating resin 24 constituting the interconnect layer 20.

Abstract translation: 半导体器件1包括互连层10,20，IC芯片30，经由插头42,44，密封树脂50和焊球60.互连层10包括通孔塞42.通孔插塞42的端面 在互连层20一侧的面积比相对端面即IC芯片30一侧的端面的面积小。在互连层10一侧的通路插塞44的端面较小 构成互连层10的绝缘树脂14的热分解温度高于构成互连层20的绝缘树脂24的热分解温度。

公开(公告)号：US07928001B2

公开(公告)日：2011-04-19

申请号：US11865750

申请日：2007-10-02

Applicant: Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

Inventor： Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

IPC: H01L21/4763

CPC classification number: H01L23/3128 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: The electronic device includes a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the lower surface of the first interconnect layer. The first interconnect layer includes a via plug (first conductive plug). An end face of the via plug on the side of the second interconnect layer is smaller in area than the opposite end face. The via plug is exposed on the surface of the first interconnect layer facing the second interconnect layer. An insulating resin forming the first interconnect layer is higher in thermal decomposition temperature than an insulating resin forming the second interconnect layer.

Abstract translation: 电子设备包括第一互连层和第二互连层。 第二互连层设置在第一互连层的下表面上。 第一互连层包括通孔插头（第一导电插头）。 通孔塞在第二互连层一侧的端面的面积小于相对端面。 通孔插头暴露在面向第二互连层的第一互连层的表面上。 形成第一互连层的绝缘树脂的热分解温度高于形成第二互连层的绝缘树脂。

公开(公告)号：US07889514B2

公开(公告)日：2011-02-15

申请号：US11544732

申请日：2006-10-10

Applicant: Shintaro Yamamichi ,  Katsumi Kikuchi ,  Yoichiro Kurita ,  Koji Soejima

Inventor： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Yoichiro Kurita ,  Koji Soejima

IPC: H05K1/11

CPC classification number: H01L23/49816 ,  H01L21/6835 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device comprising a flat wiring board, a first LSI disposed on one surface of the wiring board, a sealing resin for covering the one surface and a side face of the first semiconductor element, and a second LSI disposed on another surface of the wiring board. The wiring board has conductive wiring as a wiring layer, an insulation resin as a support layer for the wiring layer, and a conductive through-hole that passes through the wiring layer and the support layer. Connection points between lands disposed in positions in which the external peripheral edges of the semiconductor elements transverse the interior of the lands as viewed vertically from above, which lands are selected from land portions on which the external connection terminals are formed, and the wiring board formed in the same plane as the lands, are unevenly distributed toward one side of the wiring board. Connections for very small wiring are thereby made possible, and a plurality of semiconductor elements can be very densely connected.

Abstract translation: 一种半导体器件，包括平面布线板，布置在所述布线板的一个表面上的第一LSI，用于覆盖所述一个表面的密封树脂和所述第一半导体元件的侧面，以及设置在所述布线的另一个表面上的第二LSI 板。 布线基板具有作为布线层的导电布线，作为布线层的支撑层的绝缘树脂，以及穿过布线层和支撑层的导电性通孔。 半导体元件的外周边缘从上方垂直观察到的焊盘的内部的位置之间的连接点，其中所述焊盘从形成有外部连接端子的焊盘部分选择，并且形成了布线板 在与地面相同的平面中，不均匀地分布在布线板的一侧。 由此，可以实现非常小的布线的连接，并且可以非常密集地连接多个半导体元件。

公开(公告)号：US07759786B2

公开(公告)日：2010-07-20

申请号：US11543079

申请日：2006-10-05

Applicant: Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

Inventor： Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

IPC: H01L23/12

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8182 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0695

Abstract: An insulating layer 12 is formed as a surface layer of electronic circuit chip 10. A conductor interconnect 14 is formed in the insulating layer 12. The conductor interconnect 14 is exposed in the surface of the insulating layer 12. A solder wetting metallic film 16 (a metallic film) is formed on a portion of the conductor interconnect 14 to be exposed in the surface of the insulating layer 12. Typical metallic material (second metallic material) available for composing the solder wetting metallic film 16 includes a material that requires higher free energy for forming an oxide thereof, as compared with a free energy required for forming an oxide of the metallic material composing the conductor interconnect 14.

Abstract translation: 形成绝缘层12作为电子电路芯片10的表面层。导体互连14形成在绝缘层12中。导体互连14暴露在绝缘层12的表面中。焊料润湿金属膜16 金属膜）形成在导体互连14的一部分上以暴露在绝缘层12的表面中。可用于组成焊料润湿金属膜16的典型金属材料（第二金属材料）包括需要较高自由度的材料 与用于形成构成导体互连14的金属材料的氧化物所需的自由能相比，形成其氧化物的能量。

公开(公告)号：US07656046B2

公开(公告)日：2010-02-02

申请号：US11543207

申请日：2006-10-05

Applicant: Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

Inventor： Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

IPC: H01L23/28

CPC classification number: H01L21/6835 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device 1 is a semiconductor device of the BGA type, and includes a semiconductor chip 10, a resin layer 20, an insulating layer 30, and an external electrode pad 40. The resin layer 20 is constituted by a sealing resin 22 and an underfill resin 24, and covers the semiconductor chip 10. The insulating layer 30 is formed on the resin layer 20. The external electrode pad 40 is formed in the insulating layer 30. This external electrode pad 40 extends through the insulating layer 30. One surface S1 of the external electrode pad 40 is exposed in the surface of the insulating layer 30, and the other surface S2 is located in the resin layer 20. A concave portion 45 is formed in the surface S2 of the external electrode pad 40. The resin composing the resin layer 20 enters into the concave portion 45.

Abstract translation: 半导体器件1是BGA型的半导体器件，包括半导体芯片10，树脂层20，绝缘层30和外部电极焊盘40.树脂层20由密封树脂22和 底部填充树脂24并且覆盖半导体芯片10.绝缘层30形成在树脂层20上。外部电极焊盘40形成在绝缘层30中。该外部电极焊盘40延伸穿过绝缘层30.一个表面 外部电极焊盘40的S1被暴露在绝缘层30的表面中，另一个表面S2位于树脂层20中。在外部电极焊盘40的表面S2中形成有凹部45。 构成树脂层20进入凹部45。

公开(公告)号：US20090273092A1

公开(公告)日：2009-11-05

申请号：US12505011

申请日：2009-07-17

Applicant: Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

Inventor： Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

IPC: H01L23/498

CPC classification number: H01L21/6835 ,  H01L21/4853 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/83 ,  H01L24/90 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05599

Abstract: In a method for manufacturing a semiconductor module, a metal layer is formed on a support substrate. Then, first conductive posts and a first insulating layer are formed on the metal layer. The first insulating layer surrounds the sides of the first conductive posts. Then, second conductive posts are formed above the first conductive posts. The second conductive posts are electrically connected to the first conductive posts. Then, a second insulating layer is formed so as to cover the second conductive posts. The second insulating layer is made of adhesive resin. Finally, a semiconductor device is adhered to the second conductive posts by the second insulating layer while a gap between the first semiconductor device and the first insulating layer is sealed by the second insulating layer.

Abstract translation: 在半导体模块的制造方法中，在支撑基板上形成金属层。 然后，在金属层上形成第一导电柱和第一绝缘层。 第一绝缘层围绕第一导电柱的侧面。 然后，在第一导电柱上形成第二导电柱。 第二导电柱电连接到第一导电柱。 然后，形成第二绝缘层以覆盖第二导电柱。 第二绝缘层由粘合树脂制成。 最后，通过第二绝缘层将半导体器件粘附到第二导电柱，同时第一半导体器件和第一绝缘层之间的间隙被第二绝缘层密封。

公开(公告)号：US07556983B2

公开(公告)日：2009-07-07

申请号：US11345780

申请日：2006-02-02

Applicant: Yoichiro Kurita

Inventor： Yoichiro Kurita

IPC: H01L21/44

CPC classification number: H01L25/105 ,  H01L21/568 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161

Abstract: A thin, planar semiconductor device having electrodes on both surfaces is disclosed. This semiconductor device is provided with an IC chip and a wiring layer having one side that is electrically connected to surface electrodes of the IC chip. On this surface of the wiring layer, conductive posts are provided on wiring of the wiring layer, and an insulating resin covers all portions not occupied by the IC chip and conductive posts. The end surfaces of the conductive posts are exposed from the insulating resin and are used as first planar electrodes. In addition, a resist layer is formed on the opposite surface of the wiring layer. Exposed portions are formed in the resist layer to expose desired wiring portions of the wiring layer. These exposed portions are used as second planar electrodes. Stacking semiconductor devices of this construction enables an improvement in the integration of semiconductor integrated circuits.