公开(公告)号：US09871021B2

公开(公告)日：2018-01-16

申请号：US15443963

申请日：2017-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-seop Shim ,  Jaehong Kim

IPC: G11C11/34 ,  H01L25/065 ,  H01L23/498 ,  G11C16/30 ,  G11C16/10 ,  H01L23/528 ,  G11C16/08 ,  G11C16/04 ,  H01L23/00

CPC classification number: H01L25/0657 ,  G11C5/04 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30 ,  G11C29/021 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/1438 ,  H01L2924/15311

Abstract: Disclosed is a data storage device including a controller and a multi-stack chip package, and a method of operating a data storage device. The multi-stack chip package includes a first semiconductor chip arranged on a package substrate, a second semiconductor chip arranged on the first semiconductor chip, and a third semiconductor chip is arranged between the first and second semiconductor chips. The controller can control the first to third semiconductor chips by using a feature parameter measured from each semiconductor chip and a target value that may be originally designed by a memory vendor.

公开(公告)号：US09870834B2

公开(公告)日：2018-01-16

申请号：US15298171

申请日：2016-10-19

Applicant: California Institute of Technology

Inventor： Yue Li ,  Jehoshua Bruck

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/16 ,  G11C16/10 ,  G11C16/04 ,  G11C29/44 ,  G11C29/04

CPC classification number: G11C16/3495 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/16 ,  G11C29/44 ,  G11C2029/0409 ,  G11C2211/5641

Abstract: A data device includes a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme that is optional and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count.

公开(公告)号：US09870827B2

公开(公告)日：2018-01-16

申请号：US15359017

申请日：2016-11-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takashi Nakagawa ,  Hiroki Inoue ,  Fumika Akasawa ,  Yoshiyuki Kurokawa

IPC: G11C16/04 ,  G11C11/34 ,  G11C16/10 ,  H01L27/12 ,  H01L27/146

CPC classification number: G11C16/10 ,  G11C7/1006 ,  G11C7/16 ,  G11C8/12 ,  G11C11/405 ,  G11C11/4087 ,  G11C16/0466 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/14616 ,  H01L27/14636 ,  H01L27/14643

Abstract: A semiconductor device with an arithmetic processing function is provided. The semiconductor device includes a first circuit and a second circuit each having a function of performing one-dimensional discrete cosine transform. By directly inputting output data of the first circuit to the second circuit, two-dimensional discrete cosine transform can be performed immediately. A memory cell array included in the first circuit is divided into a plurality of memory blocks. In the case where a selection transistor is provided in the memory block, data processing can be performed in each memory block.

公开(公告)号：US20180012662A1

公开(公告)日：2018-01-11

申请号：US15440625

申请日：2017-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Jin SHIN ,  Ho Young SHIN

IPC: G11C16/24 ,  G11C16/30 ,  G11C16/04 ,  G11C11/4074 ,  G11C11/417

CPC classification number: G11C16/24 ,  G11C7/04 ,  G11C7/067 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/417 ,  G11C11/419 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/30 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2207/063

Abstract: A memory device includes a memory cell, a bit line connected to the memory cell, a control voltage generator configured to generate a proportional to absolute temperature (PTAT) current and generate an analog control voltage inversely proportional to the PTAT current, and a load current control circuit configured to control a first load current supplied to the bit line based on the analog control voltage.

公开(公告)号：US09858995B1

公开(公告)日：2018-01-02

申请号：US15387792

申请日：2016-12-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Tao-Yuan Lin ,  I-Chen Yang ,  Yao-Wen Chang

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C11/5642 ,  G11C11/5671 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427

Abstract: A memory device includes N word lines, wherein the word lines include an ith word line coupled to an ith memory cell and an (i+1)th word line coupled to an (i+1)th memory cell which is disposed adjacent to the ith memory cell and is a programmed memory cell, and i is an integer from 0 to (N−2). A method of operating such a memory device method includes a reading step. In the reading step, a read voltage is provided to the ith word line, a first pass voltage is provided to the (i+1)th word line, and a second pass voltage is provided to the others of the word lines, wherein the second pass voltage is lower than the first pass voltage.

公开(公告)号：US20170365340A1

公开(公告)日：2017-12-21

申请号：US15673059

申请日：2017-08-09

Applicant: Zeno Semiconductor, Inc.

Inventor： Yuniarto Widjaja

IPC: G11C14/00 ,  G11C11/404 ,  H01L29/788 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  G11C16/04 ,  G11C16/22 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/11531 ,  H01L27/11526 ,  H01L27/11521 ,  H01L27/108 ,  H01L27/105 ,  H01L21/28 ,  H01L29/792 ,  H01L21/84 ,  H01L27/12

CPC classification number: G11C14/0018 ,  G11C11/404 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/225 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

公开(公告)号：US09837427B2

公开(公告)日：2017-12-05

申请号：US15412465

申请日：2017-01-23

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara

IPC: H01L21/8234 ,  H01L21/266 ,  H01L27/11568 ,  H01L21/311 ,  H01L21/265 ,  H01L29/66 ,  H01L21/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11573 ,  H01L21/28 ,  H01L29/792 ,  H01L29/423 ,  G11C16/04

CPC classification number: H01L27/11568 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66833 ,  H01L29/792

Abstract: Deterioration in reliability is prevented regarding a semiconductor device. The deterioration is caused when an insulating film for formation of a sidewall is embedded between gate electrodes at the time of forming sidewalls having two kinds of different widths on a substrate. A sidewall-shaped silicon oxide film is formed over each sidewall of a gate electrode of a low breakdown voltage MISFET and a pattern including a control gate electrode and a memory gate electrode. Then, a silicon oxide film beside the gate electrode is removed, and a silicon oxide film is formed on a semiconductor substrate, and then etchback is performed. Accordingly, a sidewall, formed of a silicon nitride film and the silicon oxide film, is formed beside the gate electrode, and a sidewall, formed of the silicon nitride film and the silicon oxide films, is formed beside the pattern.

公开(公告)号：US09837163B2

公开(公告)日：2017-12-05

申请号：US14491123

申请日：2014-09-19

Applicant: Kyungryun Kim ,  Goeun Jung ,  Sang-Hyun Joo ,  Kyehyun Kyung

Inventor： Kyungryun Kim ,  Goeun Jung ,  Sang-Hyun Joo ,  Kyehyun Kyung

IPC: G06F12/00 ,  G06F13/00 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3418 ,  G11C16/0466 ,  G11C16/0483

Abstract: One embodiment includes obtaining programming order information for the memory area from a first table based on address information. The programming order information indicates an order in which the memory area was programmed. The embodiment further includes determining an estimated elapsed time by accessing a second table based on the obtained programming order information. The estimated elapsed time indicating time that has elapsed since the portion of the memory area was last programmed. The embodiment includes controlling the memory based on the estimated elapsed time.

公开(公告)号：US20170330860A1

公开(公告)日：2017-11-16

申请号：US15443963

申请日：2017-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-seop SHIM ,  JAEHONG KIM

IPC: H01L25/065 ,  G11C16/08 ,  G11C16/10 ,  H01L23/498 ,  H01L23/528 ,  G11C16/04 ,  G11C16/30 ,  H01L23/00

CPC classification number: H01L25/0657 ,  G11C5/04 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30 ,  G11C29/021 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/1438 ,  H01L2924/15311

Abstract: Disclosed is a data storage device including a controller and a multi-stack chip package, and a method of operating a data storage device. The multi-stack chip package includes a first semiconductor chip arranged on a package substrate, a second semiconductor chip arranged on the first semiconductor chip, and a third semiconductor chip is arranged between the first and second semiconductor chips. The controller can control the first to third semiconductor chips by using a feature parameter measured from each semiconductor chip and a target value that may be originally designed by a memory vendor.

公开(公告)号：US09818485B2

公开(公告)日：2017-11-14

申请号：US15178135

申请日：2016-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu Oh ,  Jongha Kim ,  Junjin Kong

IPC: G11C16/16 ,  G06F12/02 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/16 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/7205 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/3445

Abstract: An erase method of a nonvolatile memory device includes setting an erase mode, and performing one of a normal erase operation and a quick erase operation according to the set erase mode. The normal erase operation is performed to set a threshold voltage of a memory cell to an erase state which is lower than a first erase verification level. The quick erase operation is performed to set a threshold voltage of a memory cell to a pseudo erase state which is lower than a second erase verification level. The second erase verification level is higher than the first erase verification level.