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公开(公告)号：US20160133718A1
公开(公告)日：2016-05-12
申请号：US14539768
申请日：2014-11-12
发明人： Guan-Wei Wu , Yao-Wen Chang , I-Chen Yang , Tao-Cheng Lu
IPC分类号： H01L29/66
CPC分类号： H01L29/6656 , H01L21/26506 , H01L21/26586 , H01L21/26593 , H01L29/1083 , H01L29/6653 , H01L29/66575 , H01L29/78
摘要： Provided is a semiconductor device. Two stack layers are disposed on a substrate of a first conductivity type. Each of stack layers includes a dielectric layer and a conductive layer. The dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. First doped region of a second conductivity type has a first dopant and is disposed in the substrate between the stack layers. A pre-amorphization implantation (PAI) region is disposed in the first doped region. A second doped region of the second conductivity type has a second dopant and is disposed in the PAI region. The first conductivity type is different from the second conductivity type. A diffusion rate of the second dopant is faster than a diffusion rate of the first dopant, and a thermal activation of the second dopant is higher than that of the first dopant.
摘要翻译： 提供一种半导体器件。 两个堆叠层设置在第一导电类型的衬底上。 每个堆叠层包括电介质层和导电层。 电介质层设置在基板上。 导电层设置在电介质层上。 第二导电类型的第一掺杂区具有第一掺杂剂并且被布置在堆叠层之间的衬底中。 在第一掺杂区域中设置预非晶化注入（PAI）区域。 第二导电类型的第二掺杂区域具有第二掺杂剂并且被布置在PAI区域中。 第一导电类型与第二导电类型不同。 第二掺杂剂的扩散速度比第一掺杂剂的扩散速度快，并且第二掺杂剂的热激活高于第一掺杂剂的扩散速率。
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公开(公告)号：US20150200306A1
公开(公告)日：2015-07-16
申请号：US14154991
申请日：2014-01-14
发明人： Guan-Wei Wu , Yao-Wen Chang , I-Chen Yang , Tao-Cheng Lu
IPC分类号： H01L29/792 , H01L21/266 , H01L21/28 , H01L29/51 , H01L29/66
CPC分类号： H01L29/792 , H01L29/40117 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66833
摘要： A non-volatile memory includes a substrate, a charge trapping structure disposed on the substrate, a buffer layer disposed on the charge trapping structure, and a plurality of conductive layers disposed on the buffer layer.
摘要翻译： 非易失性存储器包括衬底，设置在衬底上的电荷俘获结构，设置在电荷俘获结构上的缓冲层和设置在缓冲层上的多个导电层。
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公开(公告)号：US08748963B1
公开(公告)日：2014-06-10
申请号：US13707426
申请日：2012-12-06
发明人： Guan-Wei Wu , I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： H01L21/4763
CPC分类号： H01L29/792 , H01L29/42352 , H01L29/66833
摘要： A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory including a gate structure disposed on a substrate, doped regions, charge storage layers, and a first dielectric layer. There are recesses in the substrate at two sides of the gate structure. The gate structure includes a gate dielectric layer disposed on the substrate and a gate disposed on the gate dielectric layer. There is an interface between the gate dielectric layer and the substrate. The doped regions are disposed in the substrate around the recesses. The charge storage layers are disposed in the recesses, and a top surface of each of the charge storage layers is higher than the interface. The first dielectric layer is disposed between the charge storage layers and the substrate, and between the charge storage layers and the gate structure.
摘要翻译： 提供了一种非易失性存储器及其制造方法。 非易失性存储器包括设置在衬底上的栅极结构，掺杂区域，电荷存储层和第一介电层。 栅极结构两侧的基板上有凹槽。 栅极结构包括设置在衬底上的栅极电介质层和设置在栅极介电层上的栅极。 在栅介电层和衬底之间存在界面。 掺杂区域围绕凹部设置在基板中。 电荷存储层设置在凹部中，并且每个电荷存储层的顶表面高于界面。 第一介电层设置在电荷存储层与基板之间，电荷存储层与栅极结构之间。
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公开(公告)号：US11823751B2
公开(公告)日：2023-11-21
申请号：US17679170
申请日：2022-02-24
发明人： Guan-Wei Wu , Yao-Wen Chang , I-Chen Yang
CPC分类号： G11C16/3459 , G11C16/0433 , G11C16/08 , G11C16/102 , G11C16/24 , G11C16/28 , G11C16/30
摘要： A memory device and an operation method thereof are provided. The operation method includes: when a read operation or a write-verify operation is completed, during a word line voltage lowering phase, synchronously applying a plurality of different gradually lowering signal line reference voltages to a plurality of ground select lines and a plurality of string select lines, wherein values of the different gradually lowering signal line reference voltages are corresponding to a plurality of signal line positions of the ground select lines and the string select lines.
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公开(公告)号：US20190067246A1
公开(公告)日：2019-02-28
申请号：US15683850
申请日：2017-08-23
发明人： Guan-Wei Wu , Chu-Yung Liu , Yao-Wen Chang , I-Chen Yang
IPC分类号： H01L25/065 , H01L21/02 , H01L21/768
摘要： A semiconductor structure includes a substrate, a stack of alternate conductive layers and insulating layers, a hole, and an active structure. The stack is disposed on the substrate. The conductive layers include an ith conductive layer and a jth conductive layer disposed above the ith conductive layer, the ith conductive layer has a thickness ti, the jth conductive layer has a thickness tj, and tj is larger than ti. The hole penetrates through the stack. The hole has a diameter Di and a diameter Dj corresponding to the ith conductive layer and the jth conductive layer, respectively, and Dj is larger than Di. The active structure is disposed in the hole. The active structure includes a channel layer. The channel layer is disposed along a sidewall of the hole and isolated from the conductive layers of the stack.
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公开(公告)号：US20180158950A1
公开(公告)日：2018-06-07
申请号：US15371293
申请日：2016-12-07
发明人： Yung-Hsiang Chen , Yao-Wen Chang , Chu-Yung Liu , I-Chen Yang , Hsin-Wen Chang
IPC分类号： H01L29/78 , H01L29/08 , H01L29/10 , H01L29/06 , H01L27/088 , H01L27/112
CPC分类号： H01L29/7838 , H01L27/11286 , H01L29/0623 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a first source/drain region, a second source/drain region, a channel doping region, a gate structure, a first well and a second well. The second source/drain region is disposed opposite to the first source/drain region. The channel doping region is disposed between the first source/drain region and the second source/drain region. The gate structure is disposed on the channel doping region. The first well has a first portion disposed under the first source/drain region. The second well is disposed opposite to the first well and separated from the second source/drain region. The first source/drain region, the second source/drain region and the channel doping region have a first conductive type. The first well and the second well have a second conductive type different from the first conductive type.
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公开(公告)号：US09208892B2
公开(公告)日：2015-12-08
申请号：US13943691
申请日：2013-07-16
发明人： Guan-Wei Wu , Yao-Wen Chang , I-Chen Yang , Tao-Cheng Lu
CPC分类号： G11C16/26 , G11C16/0475 , G11C16/3422
摘要： An operation method of a multi-level memory is provided. A first read voltage lower than a standard read voltage is applied to a doped region in a substrate at one side of a control gate of the memory, so as to determine whether a first storage position and a second storage position are both at the lowest level.
摘要翻译： 提供了多级存储器的操作方法。 将低于标准读取电压的第一读取电压施加到存储器的控制栅极的一侧的衬底中的掺杂区域，以便确定第一存储位置和第二存储位置是否都处于最低级 。
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公开(公告)号：US20240243180A1
公开(公告)日：2024-07-18
申请号：US18153368
申请日：2023-01-12
发明人： I-Chen Yang , Chun Liang Lu , Yung-Hsiang Chen , Yao-Wen Chang
IPC分类号： H01L29/423 , H01L29/66 , H01L29/78
CPC分类号： H01L29/4236 , H01L29/4238 , H01L29/66621 , H01L29/7833 , H01L29/66598
摘要： A semiconductor device includes a substrate, a gate structure, a first doped region and a second doped region. The substrate has a plurality of recesses therein. A gate structure covers the plurality of recesses and a surface of the substrate between the plurality of recesses. The gate structure includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer covers bottom surfaces and sidewalls of the plurality of recesses and the surface of the substrate between the plurality of recesses. The gate conductive layer is formed on the gate dielectric layer, fills in the plurality of recesses and covers the surface of the substrate between the plurality of recesses. The first doped region and the second doped region are located at two sides of the gate structure.
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公开(公告)号：US20190035930A1
公开(公告)日：2019-01-31
申请号：US15664010
申请日：2017-07-31
发明人： Yung-Hsiang Chen , I-Chen Yang
IPC分类号： H01L29/78 , H01L29/08 , H01L21/266
摘要： A semiconductor structure includes a substrate, a first source/drain region, a second source/drain region, a channel doping region and a gate structure. The first source/drain region is disposed in the substrate. The first source/drain region includes a first region and a second region under the first region. The second source/drain region is disposed in the substrate. The second source/drain region is disposed opposite to the first source/drain region. The channel doping region is disposed in the substrate between the first source/drain region and the second source/drain region. The gate structure is disposed on the channel doping region. In a projection plane parallel to the top surface of the substrate, the second region of the first source/drain region is separated from the gate structure. The first source/drain region, the second source/drain region and the channel doping region have the same conductive type.
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公开(公告)号：US09460928B2
公开(公告)日：2016-10-04
申请号：US14612359
申请日：2015-02-03
发明人： Chen-Han Chou , I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： H01L21/70 , H01L21/265 , H01L21/66 , H01L29/167 , H01L27/115 , H01L21/8232
CPC分类号： H01L21/26586 , H01L21/8232 , H01L22/12 , H01L22/20 , H01L27/11521 , H01L27/11568 , H01L29/66825 , H01L29/66833
摘要： A semiconductor device manufacturing method includes preparing a wafer having projections formed on a substrate. The projections project upward from a surface of the substrate and have a height measured from the surface of the substrate. The method further includes determining an interval distribution representing a distribution of intervals between neighboring projections and calculating an implantation angle based on the height and the interval distribution. The implantation angle is an angle between a normal direction of the substrate and an implantation direction. The method also includes implanting ions at the calculated implantation angle.
摘要翻译： 半导体器件制造方法包括制备具有形成在基板上的突起的晶片。 所述突出部从所述基板的表面向上突出，并且具有从所述基板的表面测量的高度。 该方法还包括确定表示相邻投影之间的间隔的分布的间隔分布，并基于高度和间隔分布计算植入角度。 注入角度是基板的法线方向与注入方向之间的角度。 该方法还包括以所计算的植入角度注入离子。
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